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Corrected waiting on PrAcc in wait_for_pracc_rw(). Added necessary check that PrAcc is "1" before FASTDATA access.

This commit is contained in:
Drasko DRASKOVIC 2011-04-04 15:24:59 +02:00 committed by Øyvind Harboe
parent b125689459
commit bc9afcd4d1
1 changed files with 42 additions and 14 deletions
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56
src/target/mips32_pracc.c
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@ -74,6 +74,8 @@ Nico Coesel
#include "config.h" #include "config.h"
#endif #endif
#include <helper/time_support.h>
#include "mips32.h" #include "mips32.h"
#include "mips32_pracc.h" #include "mips32_pracc.h"
@ -111,16 +113,34 @@ static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info,
static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
{ {
uint32_t ejtag_ctrl; uint32_t ejtag_ctrl;
long long then = timeval_ms();
int timeout;
/* wait for the PrAcc to become "1" */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
int retval;
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("fastdata load failed");
return retval;
}
while (1) while (1)
{ {
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
ejtag_ctrl = ejtag_info->ejtag_ctrl; if (retval != ERROR_OK)
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); return retval;
if (ejtag_ctrl & EJTAG_CTRL_PRACC) if (ejtag_ctrl & EJTAG_CTRL_PRACC)
break; break;
LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR; if ( (timeout = timeval_ms()-then) > 1000 )
{
LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR;
}
} }
*ctrl = ejtag_ctrl; *ctrl = ejtag_ctrl;
@ -175,7 +195,6 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
return jtag_execute_queue(); return jtag_execute_queue();
} }
@ -184,17 +203,18 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad
uint32_t ejtag_ctrl,data; uint32_t ejtag_ctrl,data;
int offset; int offset;
struct mips_ejtag *ejtag_info = ctx->ejtag_info; struct mips_ejtag *ejtag_info = ctx->ejtag_info;
int retval;
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ctx->ejtag_info, &data); retval = mips_ejtag_drscan_32(ctx->ejtag_info, &data);
if (retval != ERROR_OK)
return retval;
/* Clear access pending bit */ /* Clear access pending bit */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
int retval;
retval = jtag_execute_queue(); retval = jtag_execute_queue();
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -250,7 +270,9 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_
address = data = 0; address = data = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address); retval = mips_ejtag_drscan_32(ejtag_info, &address);
if (retval != ERROR_OK)
return retval;
/* Check for read or write */ /* Check for read or write */
if (ejtag_ctrl & EJTAG_CTRL_PRNW) if (ejtag_ctrl & EJTAG_CTRL_PRNW)
@ -1018,11 +1040,17 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
/* next fetch to dmseg should be in FASTDATA_AREA, check */ /* next fetch to dmseg should be in FASTDATA_AREA, check */
address = 0; address = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address); retval = mips_ejtag_drscan_32(ejtag_info, &address);
if (retval != ERROR_OK)
return retval;
if (address != MIPS32_PRACC_FASTDATA_AREA) if (address != MIPS32_PRACC_FASTDATA_AREA)
return ERROR_FAIL; return ERROR_FAIL;
/* wait PrAcc pending bit for FASTDATA write */
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
/* Send the load start address */ /* Send the load start address */
val = addr; val = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
@ -1030,12 +1058,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
/* Send the load end address */ /* Send the load end address */
val = addr + (count - 1) * 4; val = addr + (count - 1) * 4;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val); mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
for (i = 0; i < count; i++) for (i = 0; i < count; i++)
{ {
/* Send the data out using fastdata (clears the access pending bit) */
if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK) if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK)
return retval; return retval;
} }
@ -1051,7 +1077,9 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
address = 0; address = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address); retval = mips_ejtag_drscan_32(ejtag_info, &address);
if (retval != ERROR_OK)
return retval;
if (address != MIPS32_PRACC_TEXT) if (address != MIPS32_PRACC_TEXT)
LOG_ERROR("mini program did not return to start"); LOG_ERROR("mini program did not return to start");