swd: Fix park bit polarity according to ADIv5.1 Supplement
Change-Id: I27293defd3f3c3bf37c9662f88689e85ba593d86 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2131 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
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@ -31,7 +31,7 @@
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#define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
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#define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
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#define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
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#define SWD_CMD_PARK (0 << 7) /* not driven by host (pull high) */
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#define SWD_CMD_PARK (1 << 7) /* driven high by host */
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/* followed by TRN, 3-bits of ACK, TRN */
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/**
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