tcl: Replace 'gdb_' prefix with 'gdb' command group
Change-Id: I0490b4c112c1a922bf77a4b37df2a630a8f6cea1 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8337 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
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@ -50,7 +50,7 @@ reset init
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# setup to debug u-boot in flash
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# setup to debug u-boot in flash
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proc uboot_debug {} {
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proc uboot_debug {} {
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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xscale vector_catch 0xFF
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xscale vector_catch 0xFF
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xscale vector_table low 1 0xe59ff018
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xscale vector_table low 1 0xe59ff018
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@ -128,7 +128,7 @@ reset_config trst_and_srst
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# GDB Setup
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# GDB Setup
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#-------------------------------------------------------------------------
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#-------------------------------------------------------------------------
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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#------------------------------------------------
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#------------------------------------------------
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# ARM SPECIFIC
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# ARM SPECIFIC
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@ -95,7 +95,7 @@ adapter srst delay 100
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jtag_ntrst_delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst
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reset_config trst_and_srst
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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targets
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targets
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nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
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nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
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@ -22,7 +22,7 @@ poll_period 1
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adapter speed 3000
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adapter speed 3000
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# Enable the target description feature
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# Enable the target description feature
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gdb_target_description enable
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gdb target_description enable
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# Add a new register in the cpu register list. This register will be
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# Add a new register in the cpu register list. This register will be
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# included in the generated target descriptor file.
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# included in the generated target descriptor file.
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@ -22,7 +22,7 @@ vdebug server $_VDEBUGHOST:$_VDEBUGPORT
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# example config listen on all interfaces, disable tcl/telnet server
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# example config listen on all interfaces, disable tcl/telnet server
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bindto 0.0.0.0
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bindto 0.0.0.0
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#gdb_port 3333
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#gdb port 3333
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#telnet_port disabled
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#telnet_port disabled
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tcl_port disabled
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tcl_port disabled
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@ -35,4 +35,4 @@ reset_config none
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# The default linker scripts provided by the eSi-RISC toolchain do not
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# The default linker scripts provided by the eSi-RISC toolchain do not
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# specify attributes on memory regions, which results in incorrect
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# specify attributes on memory regions, which results in incorrect
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# application of software breakpoints by GDB.
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# application of software breakpoints by GDB.
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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@ -181,7 +181,7 @@ proc configure_esp_xtensa_default_settings { } {
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$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
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$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
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}
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}
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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if { [info exists _FLASH_VOLTAGE] } {
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if { [info exists _FLASH_VOLTAGE] } {
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$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
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$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
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@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
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$_CHIPNAME.m31 configure -event reset-assert { }
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$_CHIPNAME.m31 configure -event reset-assert { }
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# Soft breakpoints don't currently work due to broken cache handling
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# Soft breakpoints don't currently work due to broken cache handling
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
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$_CHIPNAME.m31 configure -event reset-assert { }
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$_CHIPNAME.m31 configure -event reset-assert { }
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# Soft breakpoints don't currently work due to broken cache handling
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# Soft breakpoints don't currently work due to broken cache handling
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable
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etm config $_TARGETNAME 16 normal full etb
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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arm7_9 dbgrq enable
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arm7_9 dbgrq enable
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@ -96,7 +96,7 @@ if { $_USE_CORE == 1 } {
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set _FLASH_TARGET $_TARGETNAME_0
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set _FLASH_TARGET $_TARGETNAME_0
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}
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}
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# Backup the work area. The flash probe runs an algorithm on the target CPU.
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# Backup the work area. The flash probe runs an algorithm on the target CPU.
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# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
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# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
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$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
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$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
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set _FLASHNAME $_CHIPNAME.flash
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
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flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
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@ -144,7 +144,7 @@ proc enable_apetap {} {
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tcl_port 5555
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tcl_port 5555
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telnet_port 4444
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telnet_port 4444
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gdb_port 3333
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gdb port 3333
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if { [info exists CHIPNAME] } {
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if { [info exists CHIPNAME] } {
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global _CHIPNAME
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global _CHIPNAME
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@ -319,7 +319,7 @@ global _MAXSPEED
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adapter speed $_MAXSPEED
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adapter speed $_MAXSPEED
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gdb_breakpoint_override hard
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gdb breakpoint_override hard
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set mem inaccessible-by-default-off
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set mem inaccessible-by-default-off
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jtag_ntrst_delay 100
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jtag_ntrst_delay 100
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@ -67,4 +67,4 @@ if { $_XTENSA_NUM_CORES == 1 } {
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$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
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$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
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}
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}
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gdb_report_register_access_error enable
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gdb report_register_access_error enable
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