David Brownell <david-b@pacbell.net>:
Change layout of Thumb disassembly to work better with Thumb2: - Move opcode to the left, allowing space for four hex bytes: * after address, two spaces not one tab (taking 6 spaces) * after 2-byte opcode, four spaces before tab - Also, after opcode mnemonic use a tab not a space, to make operands line up Sample output (after some patches decoding a few 32-bit instructions): 0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000 0x00003e5e 0x601a STR r2, [r3, #0x0] 0x00003e60 0x2800 CMP r0, #0x00 0x00003e62 0xd1f3 BNE 0x00003e4c 0x00003e64 0xf008fa38 BL 0x0000c2d8 The affected lines of code now wrap at sane margins too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
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309870e414
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b71e3aff6d
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@ -1367,7 +1367,9 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
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* Might be simplest to always use the Thumb2 decoder.
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*/
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\t%#8.8" PRIx32,
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address, opcode, mnemonic, target_address);
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instruction->info.b_bl_bx_blx.reg_operand = -1;
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instruction->info.b_bl_bx_blx.target_address = target_address;
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@ -1403,14 +1405,16 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
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{
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instruction->info.data_proc.variant = 0; /*immediate*/
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instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #%d",
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d",
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address, opcode, mnemonic, Rd, Rn, Rm_imm);
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}
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else
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{
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instruction->info.data_proc.variant = 1; /*immediate shift*/
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instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, r%i",
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i",
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address, opcode, mnemonic, Rd, Rn, Rm_imm);
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}
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@ -1455,7 +1459,8 @@ int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
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instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #0x%02x" ,
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%#2.2x" ,
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address, opcode, mnemonic, Rd, Rm, imm);
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return ERROR_OK;
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@ -1496,7 +1501,8 @@ int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruct
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break;
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, #%#2.2x",
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address, opcode, mnemonic, Rd, imm);
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return ERROR_OK;
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@ -1548,18 +1554,28 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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if (H1)
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{
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instruction->type = ARM_BLX;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBLX r%i", address, opcode, Rm);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32
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" 0x%4.4x \tBLX\tr%i",
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address, opcode, Rm);
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}
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else
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{
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instruction->type = ARM_BX;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBX r%i", address, opcode, Rm);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32
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" 0x%4.4x \tBX\tr%i",
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address, opcode, Rm);
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}
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}
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else
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{
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32
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" 0x%4.4x \t"
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"UNDEFINED INSTRUCTION",
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address, opcode);
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}
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return ERROR_OK;
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break;
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@ -1655,7 +1671,8 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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}
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i",
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i",
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address, opcode, mnemonic, Rd, Rm);
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return ERROR_OK;
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@ -1669,7 +1686,9 @@ int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instructi
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instruction->type = ARM_LDR;
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immediate = opcode & 0x000000ff;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tLDR r%i, [PC, #0x%" PRIx32 "]", address, opcode, Rd, immediate*4);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tLDR\tr%i, [pc, #%#" PRIx32 "]",
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address, opcode, Rd, immediate*4);
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = 15 /*PC*/;
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@ -1724,7 +1743,9 @@ int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruc
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break;
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [r%i, r%i]",
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address, opcode, mnemonic, Rd, Rn, Rm);
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = Rn;
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@ -1768,7 +1789,9 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
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shift = 0;
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s%c\tr%i, [r%i, #%#" PRIx32 "]",
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address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = Rn;
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@ -1797,7 +1820,9 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
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mnemonic = "STR";
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [SP, #%#" PRIx32 "]",
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address, opcode, mnemonic, Rd, offset*4);
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = 13 /*SP*/;
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@ -1829,7 +1854,9 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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Rn = 15;
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tADD r%i, %s, #0x%" PRIx32 "", address, opcode, Rd,reg_name, imm*4);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tADD\tr%i, %s, #%#" PRIx32,
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address, opcode, Rd, reg_name, imm * 4);
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instruction->info.data_proc.variant = 0 /* immediate */;
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instruction->info.data_proc.Rd = Rd;
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@ -1857,7 +1884,9 @@ int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instructi
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mnemonic = "ADD";
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}
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s SP, #0x%" PRIx32 "", address, opcode, mnemonic, imm*4);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\tSP, #%#" PRIx32,
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address, opcode, mnemonic, imm*4);
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instruction->info.data_proc.variant = 0 /* immediate */;
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instruction->info.data_proc.Rd = 13 /*SP*/;
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@ -1873,7 +1902,9 @@ int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction
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instruction->type = ARM_BKPT;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32 "",
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address, opcode, imm);
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return ERROR_OK;
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}
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@ -1936,7 +1967,9 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
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else /* invalid op : no registers */
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reg_names[0] = '\0';
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \t%s\t%s{%s}",
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address, opcode, mnemonic, ptr_name, reg_names);
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instruction->info.load_store_multiple.register_list = reg_list;
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instruction->info.load_store_multiple.Rn = Rn;
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@ -1955,14 +1988,16 @@ int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instructio
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{
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instruction->type = ARM_SWI;
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tSVC 0x%02" PRIx32,
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"0x%8.8" PRIx32 " 0x%4.4x \tSVC\t%#2.2" PRIx32,
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address, opcode, offset);
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return ERROR_OK;
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}
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else if (cond == 0xe)
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{
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
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address, opcode);
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return ERROR_OK;
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}
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@ -1972,7 +2007,9 @@ int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instructio
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target_address = address + 4 + (offset << 1);
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tB%s\t%#8.8" PRIx32,
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address, opcode,
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arm_condition_strings[cond], target_address);
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instruction->type = ARM_B;
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@ -1992,7 +2029,7 @@ static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
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offset |= (opcode & 0x0200) >> 4;
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tCB%sZ r%d, %#8.8" PRIx32,
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"0x%8.8" PRIx32 " 0x%4.4x \tCB%sZ\tr%d, %#8.8" PRIx32,
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address, opcode,
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(opcode & 0x0800) ? "N" : "",
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opcode & 0x7, address + 4 + (offset << 1));
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@ -2005,7 +2042,7 @@ static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
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{
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/* added in ARMv6 */
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\t%cXT%c r%d, r%d",
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"0x%8.8" PRIx32 " 0x%4.4x \t%cXT%c\tr%d, r%d",
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address, opcode,
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(opcode & 0x0080) ? 'U' : 'S',
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(opcode & 0x0040) ? 'B' : 'H',
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@ -2020,12 +2057,12 @@ static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
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/* added in ARMv6 */
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if ((opcode & 0x0ff0) == 0x0650)
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tSETEND %s",
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"0x%8.8" PRIx32 " 0x%4.4x \tSETEND %s",
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address, opcode,
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(opcode & 0x80) ? "BE" : "LE");
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else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tCPSI%c %s%s%s",
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"0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c %s%s%s",
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address, opcode,
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(opcode & 0x0010) ? 'D' : 'E',
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(opcode & 0x0004) ? "A" : "",
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@ -2053,7 +2090,7 @@ static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
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break;
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}
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tREV%s r%d, r%d",
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"0x%8.8" PRIx32 " 0x%4.4x \tREV%s\tr%d, r%d",
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address, opcode, suffix,
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opcode & 0x7, (opcode >> 3) & 0x7);
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@ -2087,7 +2124,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
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}
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\t%s",
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"0x%8.8" PRIx32 " 0x%4.4x \t%s",
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address, opcode, hint);
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return ERROR_OK;
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@ -2107,7 +2144,7 @@ static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
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x = (opcode & 0x08) ? "T" : "E";
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tIT%s%s%s %s",
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"0x%8.8" PRIx32 " 0x%4.4x \tIT%s%s%s\t%s",
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address, opcode,
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x, y, z, arm_condition_strings[cond]);
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@ -2216,7 +2253,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION",
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"0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
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address, opcode);
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return ERROR_OK;
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}
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@ -2239,7 +2276,10 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
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if ((opcode & 0xf801) == 0xe801)
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{
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%8.8x\t"
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"UNDEFINED INSTRUCTION",
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address, opcode);
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return ERROR_OK;
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}
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else
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@ -2297,7 +2337,7 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 "\t0x%8.8x\t... 32-bit Thumb2 ...",
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"0x%8.8" PRIx32 " 0x%8.8x\t... 32-bit Thumb2 ...",
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address, opcode);
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return ERROR_OK;
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}
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