diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
index 6d4a048d9..5046cd189 100644
--- a/tcl/target/bl702.cfg
+++ b/tcl/target/bl702.cfg
@@ -34,6 +34,10 @@ $_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-
 # Internal RC ticks on 32 MHz, so this speed should be safe to use.
 adapter speed 4000
 
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and configured back early
+# in BootROM.
 $_TARGETNAME configure -event reset-assert-pre {
 	halt
 
@@ -55,6 +59,15 @@ $_TARGETNAME configure -event reset-assert-pre {
 	# Do reset
 	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
 	mmw 0x40000018 0x0 0x00000007
+
+	# Since this full software reset resets GPIO pinmux as well, we will lose access
+	# to JTAG right away after writing to register. This chip doesn't support abstract
+	# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
+	# if write was successful or not, and will print error about that. Since receiving of
+	# this error is expected, we will turn off log printing for a moment,
+	set lvl [lindex [debug_level] 1]
+	debug_level -1
 	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
-	mmw 0x40000018 0x6 0x0
+	catch {mmw 0x40000018 0x7 0x0}
+	debug_level $lvl
 }