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Merge pull request #973 from kr-sc/kr-sc/update-debug-defines-os 

Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05)
This commit is contained in:
Tim Newsome 2023-12-11 09:05:42 -08:00 committed by GitHub
parent 7c94814221 84e6a4e617
commit b5e0ec3c97
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 850 additions and 1297 deletions
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576
src/target/riscv/debug_defines.c
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@ -1,6 +1,6 @@
/* /*
* This file is auto-generated by running 'make debug_defines' in * This file is auto-generated by running 'make debug_defines' in
* https://github.com/riscv/riscv-debug-spec/ (f546ddf) * https://github.com/riscv/riscv-debug-spec/ (40b9a05)
*/ */
#include "debug_defines.h" #include "debug_defines.h"
@ -63,15 +63,15 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_1(riscv_debug_reg_ctx_t conte
} }
static const char *dtm_dtmcs_errinfo_values[8] = { static const char *dtm_dtmcs_errinfo_values[8] = {
[0] = "not implemented", [0] = "not_implemented",
[1] = "dmi error", [1] = "dmi_error",
[2] = "communication error", [2] = "communication_error",
[3] = "device error", [3] = "device_error",
[4] = "unknown" [4] = "unknown"
}; };
static const char *dtm_dtmcs_version_values[16] = { static const char *dtm_dtmcs_version_values[16] = {
[0] = "0.11", [0] = "0_11",
[1] = "1.0", [1] = "1_0",
[15] = "custom" [15] = "custom"
}; };
static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t context)
@ -219,32 +219,32 @@ static riscv_debug_reg_field_list_t dtm_dmi_get_op(riscv_debug_reg_ctx_t context
static const char *csr_dcsr_debugver_values[16] = { static const char *csr_dcsr_debugver_values[16] = {
[0] = "none", [0] = "none",
[4] = "1.0", [4] = "1_0",
[15] = "custom" [15] = "custom"
}; };
static const char *csr_dcsr_ebreakvs_values[2] = { static const char *csr_dcsr_ebreakvs_values[2] = {
[0] = "exception", [0] = "exception",
[1] = "debug mode" [1] = "debug_mode"
}; };
static const char *csr_dcsr_ebreakvu_values[2] = { static const char *csr_dcsr_ebreakvu_values[2] = {
[0] = "exception", [0] = "exception",
[1] = "debug mode" [1] = "debug_mode"
}; };
static const char *csr_dcsr_ebreakm_values[2] = { static const char *csr_dcsr_ebreakm_values[2] = {
[0] = "exception", [0] = "exception",
[1] = "debug mode" [1] = "debug_mode"
}; };
static const char *csr_dcsr_ebreaks_values[2] = { static const char *csr_dcsr_ebreaks_values[2] = {
[0] = "exception", [0] = "exception",
[1] = "debug mode" [1] = "debug_mode"
}; };
static const char *csr_dcsr_ebreaku_values[2] = { static const char *csr_dcsr_ebreaku_values[2] = {
[0] = "exception", [0] = "exception",
[1] = "debug mode" [1] = "debug_mode"
}; };
static const char *csr_dcsr_stepie_values[2] = { static const char *csr_dcsr_stepie_values[2] = {
[0] = "interrupts disabled", [0] = "interrupts_disabled",
[1] = "interrupts enabled" [1] = "interrupts_enabled"
}; };
static const char *csr_dcsr_stopcount_values[2] = { static const char *csr_dcsr_stopcount_values[2] = {
[0] = "normal", [0] = "normal",
@ -491,6 +491,36 @@ static riscv_debug_reg_field_list_t csr_dpc_get_dpc(riscv_debug_reg_ctx_t contex
return result; return result;
} }
static riscv_debug_reg_field_list_t csr_dscratch0_get_dscratch0(riscv_debug_reg_ctx_t context)
{
assert(context.DXLEN.is_set);
riscv_debug_reg_field_list_t result = {
.field = {
.name = "dscratch0",
.lsb = 0,
.msb = (context.DXLEN.value + -1),
.values = NULL
},
.get_next = NULL
};
return result;
}
static riscv_debug_reg_field_list_t csr_dscratch1_get_dscratch1(riscv_debug_reg_ctx_t context)
{
assert(context.DXLEN.is_set);
riscv_debug_reg_field_list_t result = {
.field = {
.name = "dscratch1",
.lsb = 0,
.msb = (context.DXLEN.value + -1),
.values = NULL
},
.get_next = NULL
};
return result;
}
static riscv_debug_reg_field_list_t csr_tselect_get_index(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t csr_tselect_get_index(riscv_debug_reg_ctx_t context)
{ {
assert(context.XLEN.is_set); assert(context.XLEN.is_set);
@ -660,12 +690,12 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t c
return result; return result;
} }
static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context)
{ {
assert(context.XLEN.is_set); assert(context.XLEN.is_set);
riscv_debug_reg_field_list_t result = { riscv_debug_reg_field_list_t result = {
.field = { .field = {
.name = "hcontext", .name = "data",
.lsb = 0, .lsb = 0,
.msb = (context.XLEN.value + -1), .msb = (context.XLEN.value + -1),
.values = NULL .values = NULL
@ -675,12 +705,12 @@ static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ct
return result; return result;
} }
static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t csr_mcontext_get_hcontext(riscv_debug_reg_ctx_t context)
{ {
assert(context.XLEN.is_set); assert(context.XLEN.is_set);
riscv_debug_reg_field_list_t result = { riscv_debug_reg_field_list_t result = {
.field = { .field = {
.name = "data", .name = "hcontext",
.lsb = 0, .lsb = 0,
.msb = (context.XLEN.value + -1), .msb = (context.XLEN.value + -1),
.values = NULL .values = NULL
@ -701,10 +731,10 @@ static const char *csr_mcontrol_timing_values[2] = {
static const char *csr_mcontrol_sizelo_values[4] = {}; static const char *csr_mcontrol_sizelo_values[4] = {};
static const char *csr_mcontrol_action_values[16] = { static const char *csr_mcontrol_action_values[16] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -717,12 +747,12 @@ static const char *csr_mcontrol_match_values[16] = {
[1] = "napot", [1] = "napot",
[2] = "ge", [2] = "ge",
[3] = "lt", [3] = "lt",
[4] = "mask low", [4] = "mask_low",
[5] = "mask high", [5] = "mask_high",
[8] = "not equal", [8] = "not_equal",
[9] = "not napot", [9] = "not_napot",
[12] = "not mask low", [12] = "not_mask_low",
[13] = "not mask high" [13] = "not_mask_high"
}; };
static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t context)
{ {
@ -985,10 +1015,10 @@ static const char *csr_mcontrol6_size_values[8] = {
}; };
static const char *csr_mcontrol6_action_values[16] = { static const char *csr_mcontrol6_action_values[16] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -1001,12 +1031,12 @@ static const char *csr_mcontrol6_match_values[16] = {
[1] = "napot", [1] = "napot",
[2] = "ge", [2] = "ge",
[3] = "lt", [3] = "lt",
[4] = "mask low", [4] = "mask_low",
[5] = "mask high", [5] = "mask_high",
[8] = "not equal", [8] = "not_equal",
[9] = "not napot", [9] = "not_napot",
[12] = "not mask low", [12] = "not_mask_low",
[13] = "not mask high" [13] = "not_mask_high"
}; };
static const char *csr_mcontrol6_uncertainen_values[2] = { static const char *csr_mcontrol6_uncertainen_values[2] = {
[0] = "disabled", [0] = "disabled",
@ -1282,10 +1312,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_load(riscv_debug_reg_ctx_t
static const char *csr_icount_action_values[64] = { static const char *csr_icount_action_values[64] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -1447,10 +1477,10 @@ static riscv_debug_reg_field_list_t csr_icount_get_action(riscv_debug_reg_ctx_t
static const char *csr_itrigger_action_values[64] = { static const char *csr_itrigger_action_values[64] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -1599,10 +1629,10 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_action(riscv_debug_reg_ctx_
static const char *csr_etrigger_action_values[64] = { static const char *csr_etrigger_action_values[64] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -1737,10 +1767,10 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_action(riscv_debug_reg_ctx_
static const char *csr_tmexttrigger_action_values[64] = { static const char *csr_tmexttrigger_action_values[64] = {
[0] = "breakpoint", [0] = "breakpoint",
[1] = "debug mode", [1] = "debug_mode",
[2] = "trace on", [2] = "trace_on",
[3] = "trace off", [3] = "trace_off",
[4] = "trace notify", [4] = "trace_notify",
[8] = "external0", [8] = "external0",
[9] = "external1" [9] = "external1"
}; };
@ -2002,9 +2032,9 @@ static const char *dm_dmstatus_confstrptrvalid_values[2] = {
}; };
static const char *dm_dmstatus_version_values[16] = { static const char *dm_dmstatus_version_values[16] = {
[0] = "none", [0] = "none",
[1] = "0.11", [1] = "0_11",
[2] = "0.13", [2] = "0_13",
[3] = "1.0", [3] = "1_0",
[15] = "custom" [15] = "custom"
}; };
static riscv_debug_reg_field_list_t dm_dmstatus_get_allhalted(riscv_debug_reg_ctx_t context) static riscv_debug_reg_field_list_t dm_dmstatus_get_allhalted(riscv_debug_reg_ctx_t context)
@ -2592,15 +2622,15 @@ static const char *dm_abstractcs_busy_values[2] = {
[1] = "busy" [1] = "busy"
}; };
static const char *dm_abstractcs_relaxedpriv_values[2] = { static const char *dm_abstractcs_relaxedpriv_values[2] = {
[0] = "full checks", [0] = "full_checks",
[1] = "relaxed checks" [1] = "relaxed_checks"
}; };
static const char *dm_abstractcs_cmderr_values[8] = { static const char *dm_abstractcs_cmderr_values[8] = {
[0] = "none", [0] = "none",
[1] = "busy", [1] = "busy",
[2] = "not supported", [2] = "not_supported",
[3] = "exception", [3] = "exception",
[4] = "halt/resume", [4] = "halt_resume",
[5] = "bus", [5] = "bus",
[6] = "reserved", [6] = "reserved",
[7] = "other" [7] = "other"
@ -2979,7 +3009,7 @@ static riscv_debug_reg_field_list_t dm_haltsum3_get_haltsum3(riscv_debug_reg_ctx
static const char *dm_sbcs_sbversion_values[8] = { static const char *dm_sbcs_sbversion_values[8] = {
[0] = "legacy", [0] = "legacy",
[1] = "1.0" [1] = "1_0"
}; };
static const char *dm_sbcs_sbaccess_values[8] = { static const char *dm_sbcs_sbaccess_values[8] = {
[0] = "8bit", [0] = "8bit",
@ -3578,398 +3608,6 @@ static riscv_debug_reg_field_list_t virt_priv_get_prv(riscv_debug_reg_ctx_t cont
return result; return result;
} }
static riscv_debug_reg_field_list_t dmi_sercs_get_full3(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full3",
.lsb = 9,
.msb = 9,
.values = NULL
},
.get_next = NULL
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error2(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error2",
.lsb = 8,
.msb = 8,
.values = NULL
},
.get_next = dmi_sercs_get_full3
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid2(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid2",
.lsb = 7,
.msb = 7,
.values = NULL
},
.get_next = dmi_sercs_get_error2
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full2(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full2",
.lsb = 6,
.msb = 6,
.values = NULL
},
.get_next = dmi_sercs_get_valid2
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error1(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error1",
.lsb = 5,
.msb = 5,
.values = NULL
},
.get_next = dmi_sercs_get_full2
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid1(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid1",
.lsb = 4,
.msb = 4,
.values = NULL
},
.get_next = dmi_sercs_get_error1
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full1(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full1",
.lsb = 3,
.msb = 3,
.values = NULL
},
.get_next = dmi_sercs_get_valid1
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_serialcount(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "serialcount",
.lsb = 0x1c,
.msb = 0x1f,
.values = NULL
},
.get_next = dmi_sercs_get_full1
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_serial(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "serial",
.lsb = 0x18,
.msb = 0x1a,
.values = NULL
},
.get_next = dmi_sercs_get_serialcount
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error7(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error7",
.lsb = 0x17,
.msb = 0x17,
.values = NULL
},
.get_next = dmi_sercs_get_serial
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid7(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid7",
.lsb = 0x16,
.msb = 0x16,
.values = NULL
},
.get_next = dmi_sercs_get_error7
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full7(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full7",
.lsb = 0x15,
.msb = 0x15,
.values = NULL
},
.get_next = dmi_sercs_get_valid7
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error6(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error6",
.lsb = 0x14,
.msb = 0x14,
.values = NULL
},
.get_next = dmi_sercs_get_full7
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error0(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error0",
.lsb = 2,
.msb = 2,
.values = NULL
},
.get_next = dmi_sercs_get_error6
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid6(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid6",
.lsb = 0x13,
.msb = 0x13,
.values = NULL
},
.get_next = dmi_sercs_get_error0
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full6(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full6",
.lsb = 0x12,
.msb = 0x12,
.values = NULL
},
.get_next = dmi_sercs_get_valid6
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error5(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error5",
.lsb = 0x11,
.msb = 0x11,
.values = NULL
},
.get_next = dmi_sercs_get_full6
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid5(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid5",
.lsb = 0x10,
.msb = 0x10,
.values = NULL
},
.get_next = dmi_sercs_get_error5
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full5(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full5",
.lsb = 0xf,
.msb = 0xf,
.values = NULL
},
.get_next = dmi_sercs_get_valid5
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error4(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error4",
.lsb = 0xe,
.msb = 0xe,
.values = NULL
},
.get_next = dmi_sercs_get_full5
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid4(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid4",
.lsb = 0xd,
.msb = 0xd,
.values = NULL
},
.get_next = dmi_sercs_get_error4
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full4(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full4",
.lsb = 0xc,
.msb = 0xc,
.values = NULL
},
.get_next = dmi_sercs_get_valid4
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_error3(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "error3",
.lsb = 0xb,
.msb = 0xb,
.values = NULL
},
.get_next = dmi_sercs_get_full4
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid3(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid3",
.lsb = 0xa,
.msb = 0xa,
.values = NULL
},
.get_next = dmi_sercs_get_error3
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_valid0(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "valid0",
.lsb = 1,
.msb = 1,
.values = NULL
},
.get_next = dmi_sercs_get_valid3
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sercs_get_full0(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "full0",
.lsb = 0,
.msb = 0,
.values = NULL
},
.get_next = dmi_sercs_get_valid0
};
return result;
}
static riscv_debug_reg_field_list_t dmi_sertx_get_data(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "data",
.lsb = 0,
.msb = 0x1f,
.values = NULL
},
.get_next = NULL
};
return result;
}
static riscv_debug_reg_field_list_t dmi_serrx_get_data(riscv_debug_reg_ctx_t context)
{
riscv_debug_reg_field_list_t result = {
.field = {
.name = "data",
.lsb = 0,
.msb = 0x1f,
.values = NULL
},
.get_next = NULL
};
return result;
}
riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal) riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal)
{ {
static const riscv_debug_reg_info_t debug_reg_info[] = { static const riscv_debug_reg_info_t debug_reg_info[] = {
@ -3997,6 +3635,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg
.name = "dpc", .name = "dpc",
.get_fields_head = csr_dpc_get_dpc .get_fields_head = csr_dpc_get_dpc
}, },
[CSR_DSCRATCH0_ORDINAL] = {
.name = "dscratch0",
.get_fields_head = csr_dscratch0_get_dscratch0
},
[CSR_DSCRATCH1_ORDINAL] = {
.name = "dscratch1",
.get_fields_head = csr_dscratch1_get_dscratch1
},
[CSR_TSELECT_ORDINAL] = { [CSR_TSELECT_ORDINAL] = {
.name = "tselect", .name = "tselect",
.get_fields_head = csr_tselect_get_index .get_fields_head = csr_tselect_get_index
@ -4021,14 +3667,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg
.name = "tcontrol", .name = "tcontrol",
.get_fields_head = csr_tcontrol_get_mte .get_fields_head = csr_tcontrol_get_mte
}, },
[CSR_HCONTEXT_ORDINAL] = {
.name = "hcontext",
.get_fields_head = csr_hcontext_get_hcontext
},
[CSR_SCONTEXT_ORDINAL] = { [CSR_SCONTEXT_ORDINAL] = {
.name = "scontext", .name = "scontext",
.get_fields_head = csr_scontext_get_data .get_fields_head = csr_scontext_get_data
}, },
[CSR_MCONTEXT_ORDINAL] = {
.name = "mcontext",
.get_fields_head = csr_mcontext_get_hcontext
},
[CSR_MCONTROL_ORDINAL] = { [CSR_MCONTROL_ORDINAL] = {
.name = "mcontrol", .name = "mcontrol",
.get_fields_head = csr_mcontrol_get_load .get_fields_head = csr_mcontrol_get_load
@ -4201,18 +3847,6 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg
.name = "priv", .name = "priv",
.get_fields_head = virt_priv_get_prv .get_fields_head = virt_priv_get_prv
}, },
[DMI_SERCS_ORDINAL] = {
.name = "sercs",
.get_fields_head = dmi_sercs_get_full0
},
[DMI_SERTX_ORDINAL] = {
.name = "sertx",
.get_fields_head = dmi_sertx_get_data
},
[DMI_SERRX_ORDINAL] = {
.name = "serrx",
.get_fields_head = dmi_serrx_get_data
},
}; };
return debug_reg_info[reg_ordinal]; return debug_reg_info[reg_ordinal];
} }

1529
src/target/riscv/debug_defines.h
View File

File diff suppressed because it is too large Load Diff

25
src/target/riscv/debug_reg_printer.c
View File

@ -62,22 +62,35 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field,
static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset, static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex), struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex),
riscv_debug_reg_ctx_t context, uint64_t value) riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show)
{ {
unsigned int curr = offset; unsigned int curr = offset;
curr += get_len_or_sprintf(buf, curr, " { "); curr += get_len_or_sprintf(buf, curr, " {");
char *separator = "";
for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) { for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) {
list = get_next(context); list = get_next(context);
uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
if (show == RISCV_DEBUG_REG_SHOW_ALL ||
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 &&
(field_value != 0 ||
(list.field.values && list.field.values[0]))) ||
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) {
curr += get_len_or_sprintf(buf, curr, separator);
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
riscv_debug_reg_field_value(list.field, value)); field_value);
curr += get_len_or_sprintf(buf, curr, ", "); separator = " ";
}
} }
curr += get_len_or_sprintf(buf, curr, "}"); curr += get_len_or_sprintf(buf, curr, "}");
return curr - offset; return curr - offset;
} }
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value) riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show)
{ {
unsigned int length = 0; unsigned int length = 0;
@ -88,7 +101,7 @@ unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_or
if (reg.get_fields_head) if (reg.get_fields_head)
length += riscv_debug_reg_fields_to_s(buf, length, length += riscv_debug_reg_fields_to_s(buf, length,
reg.get_fields_head, context, value); reg.get_fields_head, context, value, show);
if (buf) if (buf)
buf[length] = '\0'; buf[length] = '\0';

9
src/target/riscv/debug_reg_printer.h
View File

@ -2,6 +2,12 @@
#include "debug_defines.h" #include "debug_defines.h"
enum riscv_debug_reg_show {
RISCV_DEBUG_REG_SHOW_ALL,
RISCV_DEBUG_REG_HIDE_ALL_0,
RISCV_DEBUG_REG_HIDE_UNNAMED_0,
};
/** /**
* This function is used to fill a buffer with a decoded string representation * This function is used to fill a buffer with a decoded string representation
* of register's value. * of register's value.
@ -25,4 +31,5 @@
* riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, <dmi value>); * riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, <dmi value>);
*/ */
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value); riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show);

6
src/target/riscv/riscv-013.c
View File

@ -302,12 +302,12 @@ static void log_debug_reg(struct target *target, enum riscv_debug_reg_ordinal re
if (debug_level < LOG_LVL_DEBUG) if (debug_level < LOG_LVL_DEBUG)
return; return;
const riscv_debug_reg_ctx_t context = get_riscv_debug_reg_ctx(target); const riscv_debug_reg_ctx_t context = get_riscv_debug_reg_ctx(target);
char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value) + 1); char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1);
if (!buf) { if (!buf) {
LOG_ERROR("Unable to allocate memory."); LOG_ERROR("Unable to allocate memory.");
return; return;
} }
riscv_debug_reg_to_s(buf, reg, context, value); riscv_debug_reg_to_s(buf, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0);
log_printf_lf(LOG_LVL_DEBUG, file, line, func, "[%s] %s", target_name(target), buf); log_printf_lf(LOG_LVL_DEBUG, file, line, func, "[%s] %s", target_name(target), buf);
free(buf); free(buf);
} }
@ -356,7 +356,7 @@ static unsigned int decode_dm(char *text, unsigned int address, unsigned int dat
.abits = { .value = 0, .is_set = false }, .abits = { .value = 0, .is_set = false },
}; };
return riscv_debug_reg_to_s(text, description[i].ordinal, return riscv_debug_reg_to_s(text, description[i].ordinal,
context, data); context, data, RISCV_DEBUG_REG_HIDE_ALL_0);
} }
} }
if (text) if (text)