diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
new file mode 100644
index 000000000..af7647d87
--- /dev/null
+++ b/tcl/target/fm3.cfg
@@ -0,0 +1,47 @@
+# MB96F506
+# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME mb9bf500
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+# delays on reset lines
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+# Fujitsu cortex-M3 reset configuration
+reset_config trst_only
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# MB9BF506 has 64kB of SRAM on its main system bus 
+$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
+
+# MB9BF506 has 512kB internal FLASH 
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+
+# 4MHz / 6 = 666kHz, so use 500
+adapter_khz 500
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq