Prefix RISC-V globals with riscv_.
Also removed some stuff from riscv.h that was only used in one file anyway. Change-Id: Id980fba15448042b18b04e8da8ec48bd2d32fda8
This commit is contained in:
Tim Newsome
parent
57b57989b4
commit
b4f17d4a63
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@ -27,7 +27,7 @@ struct riscv_batch *riscv_batch_alloc(struct target *target, size_t scans, size_
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out->data_out = malloc(sizeof(*out->data_out) * (scans) * DMI_SCAN_BUF_SIZE);
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out->data_in = malloc(sizeof(*out->data_in) * (scans) * DMI_SCAN_BUF_SIZE);
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out->fields = malloc(sizeof(*out->fields) * (scans));
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if (bscan_tunnel_ir_width != 0)
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if (riscv_bscan_tunnel_ir_width != 0)
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out->bscan_ctxt = malloc(sizeof(*out->bscan_ctxt) * (scans));
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out->last_scan = RISCV_SCAN_TYPE_INVALID;
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out->read_keys = malloc(sizeof(*out->read_keys) * (scans));
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@ -62,7 +62,7 @@ int riscv_batch_run(struct riscv_batch *batch)
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riscv_batch_add_nop(batch);
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for (size_t i = 0; i < batch->used_scans; ++i) {
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if (bscan_tunnel_ir_width != 0)
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if (riscv_bscan_tunnel_ir_width != 0)
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riscv_add_bscan_tunneled_scan(batch->target, batch->fields+i, batch->bscan_ctxt+i);
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else
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jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE);
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@ -76,7 +76,7 @@ int riscv_batch_run(struct riscv_batch *batch)
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return ERROR_FAIL;
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}
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if (bscan_tunnel_ir_width != 0) {
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if (riscv_bscan_tunnel_ir_width != 0) {
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/* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
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for (size_t i = 0; i < batch->used_scans; ++i)
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buffer_shr((batch->fields + i)->in_value, DMI_SCAN_BUF_SIZE, 1);
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@ -285,7 +285,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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buf_set_u32(out_value, 0, 32, out);
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jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dtmcontrol, TAP_IDLE);
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field.num_bits = 32;
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field.out_value = out_value;
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@ -293,7 +293,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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/* Always return to dbus. */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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@ -312,7 +312,7 @@ static uint32_t idcode_scan(struct target *target)
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struct scan_field field;
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uint8_t in_value[4];
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jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_idcode, TAP_IDLE);
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field.num_bits = 32;
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field.out_value = NULL;
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@ -326,7 +326,7 @@ static uint32_t idcode_scan(struct target *target)
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}
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/* Always return to dbus. */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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uint32_t in = buf_get_u32(field.in_value, 0, 32);
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LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
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@ -1373,7 +1373,7 @@ static int set_register(struct target *target, int hartid, int regid,
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static int halt(struct target *target)
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{
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LOG_DEBUG("riscv_halt()");
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
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cache_set32(target, 1, csrr(S0, CSR_MHARTID));
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@ -1422,7 +1422,7 @@ static int strict_step(struct target *target, bool announce)
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static int step(struct target *target, int current, target_addr_t address,
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int handle_breakpoints)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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if (!current) {
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if (riscv_xlen(target) > 32) {
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@ -1876,7 +1876,7 @@ static int handle_halt(struct target *target, bool announce)
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static int poll_target(struct target *target, bool announce)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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/* Inhibit debug logging during poll(), which isn't usually interesting and
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* just fills up the screen/logs with clutter. */
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@ -1911,7 +1911,7 @@ static int riscv011_resume(struct target *target, int current,
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target_addr_t address, int handle_breakpoints, int debug_execution)
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{
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RISCV_INFO(r);
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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r->prepped = false;
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return resume(target, debug_execution, false);
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@ -1922,7 +1922,7 @@ static int assert_reset(struct target *target)
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riscv011_info_t *info = get_info(target);
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/* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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/* The only assumption we can make is that the TAP was reset. */
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if (wait_for_debugint_clear(target, true) != ERROR_OK) {
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@ -1955,7 +1955,7 @@ static int assert_reset(struct target *target)
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static int deassert_reset(struct target *target)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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if (target->reset_halt)
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return wait_for_state(target, TARGET_HALTED);
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else
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@ -1970,7 +1970,7 @@ static int read_memory(struct target *target, target_addr_t address,
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return ERROR_NOT_IMPLEMENTED;
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}
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
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switch (size) {
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@ -2134,7 +2134,7 @@ static int write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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riscv011_info_t *info = get_info(target);
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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/* Set up the address. */
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cache_set_store(target, 0, T0, SLOT1);
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@ -416,11 +416,11 @@ static void dump_field(int idle, const struct scan_field *field)
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static void select_dmi(struct target *target)
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{
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if (bscan_tunnel_ir_width != 0) {
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if (riscv_bscan_tunnel_ir_width != 0) {
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select_dmi_via_bscan(target);
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return;
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}
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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}
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static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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@ -429,12 +429,12 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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uint8_t in_value[4];
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uint8_t out_value[4] = { 0 };
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if (bscan_tunnel_ir_width != 0)
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if (riscv_bscan_tunnel_ir_width != 0)
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return dtmcontrol_scan_via_bscan(target, out);
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buf_set_u32(out_value, 0, 32, out);
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jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dtmcontrol, TAP_IDLE);
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field.num_bits = 32;
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field.out_value = out_value;
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@ -511,7 +511,7 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
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the jtag_execute_queue() call. Heap or static fields in this case doesn't seem
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the best fit. Declaring stack based field values in a subsidiary function call wouldn't
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work. */
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if (bscan_tunnel_ir_width != 0) {
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if (riscv_bscan_tunnel_ir_width != 0) {
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riscv_add_bscan_tunneled_scan(target, &field, &bscan_ctxt);
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} else {
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/* Assume dbus is already selected. */
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@ -533,7 +533,7 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
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return DMI_STATUS_FAILED;
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}
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if (bscan_tunnel_ir_width != 0) {
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if (riscv_bscan_tunnel_ir_width != 0) {
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/* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
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buffer_shr(in, num_bytes, 1);
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}
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@ -156,30 +156,34 @@ typedef enum slot {
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#define MAX_HWBPS 16
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#define DRAM_CACHE_SIZE 16
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uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
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struct scan_field select_dtmcontrol = {
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uint8_t riscv_ir_dtmcontrol[4] = {DTMCONTROL};
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struct scan_field riscv_select_dtmcontrol = {
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.in_value = NULL,
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.out_value = ir_dtmcontrol
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.out_value = riscv_ir_dtmcontrol
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};
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uint8_t ir_dbus[4] = {DBUS};
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struct scan_field select_dbus = {
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uint8_t riscv_ir_dbus[4] = {DBUS};
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struct scan_field riscv_select_dbus = {
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.in_value = NULL,
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.out_value = ir_dbus
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.out_value = riscv_ir_dbus
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};
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uint8_t ir_idcode[4] = {0x1};
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struct scan_field select_idcode = {
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uint8_t riscv_ir_idcode[4] = {0x1};
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struct scan_field riscv_select_idcode = {
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.in_value = NULL,
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.out_value = ir_idcode
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.out_value = riscv_ir_idcode
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};
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bscan_tunnel_type_t bscan_tunnel_type;
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int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
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typedef enum {
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BSCAN_TUNNEL_NESTED_TAP,
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BSCAN_TUNNEL_DATA_REGISTER
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} bscan_tunnel_type_t;
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static bscan_tunnel_type_t bscan_tunnel_type;
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int riscv_bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
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uint8_t bscan_zero[4] = {0};
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uint8_t bscan_one[4] = {1};
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uint8_t ir_user4[4];
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struct scan_field select_user4 = {
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static uint8_t ir_user4[4];
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static struct scan_field select_user4 = {
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.in_value = NULL,
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.out_value = ir_user4
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};
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@ -194,7 +198,7 @@ struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
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},
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{
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.num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
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.out_value = ir_dbus,
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.out_value = riscv_ir_dbus,
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.in_value = NULL,
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},
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{
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@ -222,7 +226,7 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
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},
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{
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.num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
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.out_value = ir_dbus,
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.out_value = riscv_ir_dbus,
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.in_value = NULL,
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},
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{
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@ -332,7 +336,7 @@ void select_dmi_via_bscan(struct target *target)
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uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
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{
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/* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
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uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
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uint8_t tunneled_ir_width[4] = {riscv_bscan_tunnel_ir_width};
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uint8_t tunneled_dr_width[4] = {32};
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uint8_t out_value[5] = {0};
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uint8_t in_value[5] = {0};
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@ -345,8 +349,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
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tunneled_ir[0].num_bits = 3;
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tunneled_ir[0].out_value = bscan_zero;
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tunneled_ir[0].in_value = NULL;
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tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
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tunneled_ir[1].out_value = ir_dtmcontrol;
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tunneled_ir[1].num_bits = riscv_bscan_tunnel_ir_width;
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tunneled_ir[1].out_value = riscv_ir_dtmcontrol;
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tunneled_ir[1].in_value = NULL;
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tunneled_ir[2].num_bits = 7;
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tunneled_ir[2].out_value = tunneled_ir_width;
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@ -372,8 +376,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
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tunneled_ir[3].num_bits = 3;
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tunneled_ir[3].out_value = bscan_zero;
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tunneled_ir[3].in_value = NULL;
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tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
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tunneled_ir[2].out_value = ir_dtmcontrol;
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tunneled_ir[2].num_bits = riscv_bscan_tunnel_ir_width;
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tunneled_ir[2].out_value = riscv_ir_dtmcontrol;
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tunneled_ir[1].in_value = NULL;
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tunneled_ir[1].num_bits = 7;
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tunneled_ir[1].out_value = tunneled_ir_width;
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@ -421,13 +425,13 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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uint8_t in_value[4];
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uint8_t out_value[4] = { 0 };
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if (bscan_tunnel_ir_width != 0)
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if (riscv_bscan_tunnel_ir_width != 0)
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return dtmcontrol_scan_via_bscan(target, out);
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buf_set_u32(out_value, 0, 32, out);
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jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dtmcontrol, TAP_IDLE);
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field.num_bits = 32;
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field.out_value = out_value;
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@ -435,7 +439,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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/* Always return to dbus. */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &riscv_select_dbus, TAP_IDLE);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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@ -480,11 +484,11 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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riscv_info_init(target, info);
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info->cmd_ctx = cmd_ctx;
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select_dtmcontrol.num_bits = target->tap->ir_length;
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select_dbus.num_bits = target->tap->ir_length;
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select_idcode.num_bits = target->tap->ir_length;
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riscv_select_dtmcontrol.num_bits = target->tap->ir_length;
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riscv_select_dbus.num_bits = target->tap->ir_length;
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riscv_select_idcode.num_bits = target->tap->ir_length;
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if (bscan_tunnel_ir_width != 0) {
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if (riscv_bscan_tunnel_ir_width != 0) {
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assert(target->tap->ir_length >= 6);
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uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
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ir_user4[0] = (uint8_t)ir_user4_raw;
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@ -492,11 +496,11 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
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ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
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select_user4.num_bits = target->tap->ir_length;
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bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
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bscan_tunneled_ir_width[0] = riscv_bscan_tunnel_ir_width;
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if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
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bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
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bscan_tunnel_data_register_select_dmi[1].num_bits = riscv_bscan_tunnel_ir_width;
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else /* BSCAN_TUNNEL_NESTED_TAP */
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bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
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bscan_tunnel_nested_tap_select_dmi[2].num_bits = riscv_bscan_tunnel_ir_width;
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}
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riscv_semihosting_init(target);
|
||||
|
|
@ -2568,11 +2572,11 @@ COMMAND_HANDLER(riscv_set_ir)
|
|||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
|
||||
|
||||
if (!strcmp(CMD_ARGV[0], "idcode"))
|
||||
buf_set_u32(ir_idcode, 0, 32, value);
|
||||
buf_set_u32(riscv_ir_idcode, 0, 32, value);
|
||||
else if (!strcmp(CMD_ARGV[0], "dtmcs"))
|
||||
buf_set_u32(ir_dtmcontrol, 0, 32, value);
|
||||
buf_set_u32(riscv_ir_dtmcontrol, 0, 32, value);
|
||||
else if (!strcmp(CMD_ARGV[0], "dmi"))
|
||||
buf_set_u32(ir_dbus, 0, 32, value);
|
||||
buf_set_u32(riscv_ir_dbus, 0, 32, value);
|
||||
else
|
||||
return ERROR_FAIL;
|
||||
|
||||
|
|
@ -2620,7 +2624,7 @@ COMMAND_HANDLER(riscv_use_bscan_tunnel)
|
|||
LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
|
||||
|
||||
bscan_tunnel_type = tunnel_type;
|
||||
bscan_tunnel_ir_width = irwidth;
|
||||
riscv_bscan_tunnel_ir_width = irwidth;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -219,21 +219,11 @@ static inline riscv_info_t *riscv_info(const struct target *target)
|
|||
{ return target->arch_info; }
|
||||
#define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
|
||||
|
||||
extern uint8_t ir_dtmcontrol[4];
|
||||
extern struct scan_field select_dtmcontrol;
|
||||
extern uint8_t ir_dbus[4];
|
||||
extern struct scan_field select_dbus;
|
||||
extern uint8_t ir_idcode[4];
|
||||
extern struct scan_field select_idcode;
|
||||
extern struct scan_field riscv_select_dtmcontrol;
|
||||
extern struct scan_field riscv_select_dbus;
|
||||
extern struct scan_field riscv_select_idcode;
|
||||
|
||||
extern struct scan_field select_user4;
|
||||
extern struct scan_field *bscan_tunneled_select_dmi;
|
||||
extern uint32_t bscan_tunneled_select_dmi_num_fields;
|
||||
extern uint8_t bscan_zero[4];
|
||||
extern uint8_t bscan_one[4];
|
||||
typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
|
||||
extern int bscan_tunnel_ir_width;
|
||||
extern bscan_tunnel_type_t bscan_tunnel_type;
|
||||
extern int riscv_bscan_tunnel_ir_width;
|
||||
|
||||
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
|
||||
void select_dmi_via_bscan(struct target *target);
|
||||
|
|
|
|||
Loading…
Reference in New Issue