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at91sam3: Added support for at91sam3sd8a and b 

This update is untested due to missing hardware.

Change-Id: Ibe286b741ebbb1c8ae0bd3dea4b8f3e12320ab34
Signed-off-by: Ulf Wetzker <ulf.wetzker@eas.iis.fraunhofer.de>
Reviewed-on: http://openocd.zylin.com/1423
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Ulf Wetzker 2013-05-27 13:21:07 +02:00 committed by Spencer Oliver
parent 8d70c86200
commit b3d4a44686
1 changed files with 81 additions and 1 deletions
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82
src/flash/nor/at91sam3.c
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@ -569,7 +569,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* Note: The preliminary at91sam3s datasheet says on page 302 */ /* Note: The preliminary at91sam3s datasheet says on page 302 */
/* that the flash controller is at address 0x400E0800. */ /* that the flash controller is at address 0x400E0800. */
/* This is _not_ the case, the controller resides at address 0x400e0a0. */ /* This is _not_ the case, the controller resides at address 0x400e0a00. */
{ {
.chipid_cidr = 0x28A00960, .chipid_cidr = 0x28A00960,
.name = "at91sam3s4c", .name = "at91sam3s4c",
@ -731,6 +731,86 @@ static const struct sam3_chip_details all_sam3_details[] = {
}, },
}, },
}, },
{
.chipid_cidr = 0x298B0A60,
.name = "at91sam3sd8a",
.total_flash_size = 512 * 1024,
.total_sram_size = 64 * 1024,
.n_gpnvms = 3,
.n_banks = 2,
{
/* .bank[0] = { */
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
.sector_size = 32768,
.page_size = 256,
},
/* .bank[1] = { */
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
.sector_size = 32768,
.page_size = 256,
},
},
},
{
.chipid_cidr = 0x299B0A60,
.name = "at91sam3sd8b",
.total_flash_size = 512 * 1024,
.total_sram_size = 64 * 1024,
.n_gpnvms = 3,
.n_banks = 2,
{
/* .bank[0] = { */
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
.sector_size = 32768,
.page_size = 256,
},
/* .bank[1] = { */
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
.sector_size = 32768,
.page_size = 256,
},
},
},
{ {
.chipid_cidr = 0x29ab0a60, .chipid_cidr = 0x29ab0a60,
.name = "at91sam3sd8c", .name = "at91sam3sd8c",