flash/nor/nrf5: implement BPROT protection check for nRF52810,832
Also refuse 'flash protect' on any nRF52. Fail protection check on nRF52840 until ACL protection is implemented. Change-Id: I84fcf117427e4894147c3ad92e2a3597566b4fcf Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4864 Tested-by: jenkins
This commit is contained in:
Tomas Vanek
parent
5da746fa09
commit
b2dbaf9e15
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@ -103,6 +103,8 @@ enum nrf5_nvmc_registers {
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NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
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NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
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NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
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NRF5_BPROT_BASE = 0x40000000,
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};
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enum nrf5_nvmc_config_bits {
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@ -120,12 +122,20 @@ struct nrf52_ficr_info {
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uint32_t flash;
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};
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enum nrf5_features {
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NRF5_FEATURE_SERIES_51 = 1 << 0,
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NRF5_FEATURE_SERIES_52 = 1 << 1,
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NRF5_FEATURE_BPROT = 1 << 2,
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NRF5_FEATURE_ACL_PROT = 1 << 3,
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};
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struct nrf5_device_spec {
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uint16_t hwid;
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const char *part;
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const char *variant;
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const char *build_code;
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unsigned int flash_size_kb;
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enum nrf5_features features;
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};
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struct nrf5_info {
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@ -142,16 +152,28 @@ struct nrf5_info {
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struct nrf52_ficr_info ficr_info;
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const struct nrf5_device_spec *spec;
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uint32_t hwid;
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enum nrf5_features features;
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unsigned int flash_size_kb;
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};
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#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
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#define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
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{ \
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.hwid = (id), \
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.part = pt, \
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.variant = var, \
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.build_code = bcode, \
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.flash_size_kb = (fsize), \
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.features = NRF5_FEATURE_SERIES_51, \
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}
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#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
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{ \
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.hwid = (id), \
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.part = pt, \
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.variant = var, \
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.build_code = bcode, \
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.flash_size_kb = (fsize), \
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.features = features, \
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}
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/* The known devices table below is derived from the "nRF5x series
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@ -173,73 +195,73 @@ struct nrf5_info {
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*/
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static const struct nrf5_device_spec nrf5_known_devices_table[] = {
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/* nRF51822 Devices (IC rev 1). */
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NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
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NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
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NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
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NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
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NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
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NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
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NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
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NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
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NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
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NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
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/* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
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with built-in jlink seem to use engineering samples not listed
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in the nRF51 Series Compatibility Matrix V1.0. */
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NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
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NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
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/* nRF51822 Devices (IC rev 2). */
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NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
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NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
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NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
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NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
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NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
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NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
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NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
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NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
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NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
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NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
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NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
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NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
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NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
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NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
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NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
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NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
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NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
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NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
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/* nRF51822 Devices (IC rev 3). */
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NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
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NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
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NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
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NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
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NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
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NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
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NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
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NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
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NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
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NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
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NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
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NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
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NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
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NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
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NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
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NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
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NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
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NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
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/* nRF51422 Devices (IC rev 1). */
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NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
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NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
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NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
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NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
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NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
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NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
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/* nRF51422 Devices (IC rev 2). */
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NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
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NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
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NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
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NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
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NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
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NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
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NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
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NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
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/* nRF51422 Devices (IC rev 3). */
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NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
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NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
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NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
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NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
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NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
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NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
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NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
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NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
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NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
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NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
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NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
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NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
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NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
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NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
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/* The driver fully autodects nRF52 series devices by FICR INFO,
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* no need for nRF52xxx HWIDs in this table */
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#if 0
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/* nRF52810 Devices */
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NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192),
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NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192),
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NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
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NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
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/* nRF52832 Devices */
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NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
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NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
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NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512),
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NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
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NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
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NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
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/* nRF52840 Devices */
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NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024),
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NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
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#endif
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};
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@ -408,6 +430,33 @@ error:
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return ERROR_FAIL;
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}
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static int nrf5_protect_check_bprot(struct flash_bank *bank)
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{
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struct nrf5_bank *nbank = bank->driver_priv;
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struct nrf5_info *chip = nbank->chip;
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assert(chip != NULL);
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static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
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uint32_t bprot_reg = 0;
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int res;
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for (int i = 0; i < bank->num_sectors; i++) {
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unsigned int bit = i % 32;
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if (bit == 0) {
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unsigned int n_reg = i / 32;
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if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
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break;
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res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
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if (res != ERROR_OK)
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return res;
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}
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bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
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}
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return ERROR_OK;
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}
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static int nrf5_protect_check(struct flash_bank *bank)
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{
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int res;
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@ -422,6 +471,14 @@ static int nrf5_protect_check(struct flash_bank *bank)
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assert(chip != NULL);
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if (chip->features & NRF5_FEATURE_BPROT)
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return nrf5_protect_check_bprot(bank);
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if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
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LOG_WARNING("Flash protection of this nRF device is not supported");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
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&clenr0);
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if (res != ERROR_OK) {
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@ -459,6 +516,11 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
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if (res != ERROR_OK)
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return res;
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if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
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LOG_ERROR("Flash protection setting of this nRF device is not supported");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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if (first != 0) {
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LOG_ERROR("Code region 0 must start at the begining of the bank");
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return ERROR_FAIL;
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@ -564,7 +626,27 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
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}
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uint32_t series = chip->ficr_info.part & 0xfffff000;
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if (!(series == 0x51000 || series == 0x52000)) {
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switch (series) {
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case 0x51000:
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chip->features = NRF5_FEATURE_SERIES_51;
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break;
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case 0x52000:
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chip->features = NRF5_FEATURE_SERIES_52;
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switch (chip->ficr_info.part) {
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case 0x52810:
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case 0x52832:
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chip->features |= NRF5_FEATURE_BPROT;
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break;
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case 0x52840:
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chip->features |= NRF5_FEATURE_ACL_PROT;
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break;
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}
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break;
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default:
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LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
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PRIx32, chip->ficr_info.part);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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@ -612,18 +694,22 @@ static int nrf5_probe(struct flash_bank *bank)
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chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
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* bytes of the CONFIGID register */
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chip->spec = NULL;
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for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
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if (chip->hwid == nrf5_known_devices_table[i].hwid) {
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chip->spec = &nrf5_known_devices_table[i];
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break;
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}
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}
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/* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
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chip->features = NRF5_FEATURE_SERIES_51;
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/* Don't bail out on error for the case that some old engineering
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* sample has FICR INFO registers unreadable. We can proceed anyway. */
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(void)nrf5_read_ficr_info(chip);
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chip->spec = NULL;
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for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
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if (chip->hwid == nrf5_known_devices_table[i].hwid) {
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chip->spec = &nrf5_known_devices_table[i];
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chip->features = chip->spec->features;
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break;
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}
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}
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if (chip->spec && chip->ficr_info_valid) {
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/* check if HWID table gives the same part as FICR INFO */
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if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
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@ -661,7 +747,6 @@ static int nrf5_probe(struct flash_bank *bank)
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}
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}
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if (bank->base == NRF5_FLASH_BASE) {
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bank->num_sectors = num_sectors;
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bank->size = num_sectors * flash_page_size;
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