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Use a wall clock timeout to complete reset.

This commit is contained in:
Tim Newsome 2017-07-16 11:16:49 -07:00
parent f0f1df1061
commit b032eb1bcc
1 changed files with 9 additions and 5 deletions
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14
src/target/riscv/riscv-013.c
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@ -121,7 +121,8 @@ typedef enum slot {
/*** Info about the core being debugged. ***/ /*** Info about the core being debugged. ***/
#define WALL_CLOCK_TIMEOUT 2 #define WALL_CLOCK_TIMEOUT 2
#define WALL_CLOCK_RESET_TIMEOUT 30
struct trigger { struct trigger {
uint64_t address; uint64_t address;
@ -1882,14 +1883,17 @@ void riscv013_reset_current_hart(struct target *target)
control = set_field(control, DMI_DMCONTROL_NDMRESET, 0); control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
dmi_write(target, DMI_DMCONTROL, control); dmi_write(target, DMI_DMCONTROL, control);
for (unsigned i = 0; i < 256; i++) { time_t start = time(NULL);
while (1) {
uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS); uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS);
if (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED)) { if (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED)) {
break; break;
} }
if (i == 255) { if (time(NULL) - start > WALL_CLOCK_RESET_TIMEOUT) {
LOG_ERROR("Hart didn't halt coming out of reset; dmstatus=0x%x", LOG_ERROR("Hart didn't halt coming out of reset in %ds; "
dmstatus); "dmstatus=0x%x", WALL_CLOCK_RESET_TIMEOUT, dmstatus);
return;
} }
} }