interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

doc: fix OpenRISC target documentation 

OpenRISC correct target name is 'or1k' not 'openrisc'
http://openocd.zylin.com/3096 introduced a conflict between 'openrisc'
and 'ls1_sap' documentations

Change-Id: Iedebbf9809300e1272334c5b63d0b31a41062282
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5485
Tested-by: jenkins
Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI 2020-03-02 13:58:07 +01:00 committed by Oleksij Rempel
parent f00070edaf
commit af69f5ad0b
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
doc/openocd.texi
View File

@ -4434,10 +4434,10 @@ The current implementation supports eSi-32xx cores.
@item @code{mips_m4k} -- a MIPS core
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
@item @code{openrisc} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores:
@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
allowing access to physical memory addresses independently of CPU cores.
@item @code{or1k} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores:
@itemize @minus
@item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
@item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})