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Checkpoint: fix even more code style issues

This commit is contained in:
Ryan Macdonald 2018-04-05 16:49:00 -07:00
parent 8c8bed878c
commit ada78cae11
1 changed files with 13 additions and 14 deletions
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27
src/target/riscv/riscv-013.c
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@ -2827,17 +2827,17 @@ static int get_max_sbaccess(struct target *target)
uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8);
if (sbaccess128) if (sbaccess128)
return 4; return 4;
else if (sbaccess64) else if (sbaccess64)
return 3; return 3;
else if (sbaccess32) else if (sbaccess32)
return 2; return 2;
else if (sbaccess16) else if (sbaccess16)
return 1; return 1;
else if (sbaccess8) else if (sbaccess8)
return 0; return 0;
else else
return ERROR_FAIL; return ERROR_FAIL;
} }
static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address)
@ -2887,7 +2887,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill
} }
} }
if (test_passed) if (test_passed)
LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED");
// Test 2: Simple write/read test, with address autoincrement // Test 2: Simple write/read test, with address autoincrement
test_passed = true; test_passed = true;
@ -2923,7 +2923,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill
} }
} }
if (test_passed) if (test_passed)
LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED");
// Test 3: Read from illegal address // Test 3: Read from illegal address
read_memory_sba_simple(target, illegal_address, sbcs_orig); read_memory_sba_simple(target, illegal_address, sbcs_orig);
@ -3014,11 +3014,10 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill
sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1);
dmi_write(target, DMI_SBCS, sbcs); dmi_write(target, DMI_SBCS, sbcs);
dmi_read(target, &rd_val, DMI_SBCS); dmi_read(target, &rd_val, DMI_SBCS);
if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) { if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0)
LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED");
} else { else
LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0");
}
} else { } else {
LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set");
} }