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target aarch64: rework memory read/write to use 8/16/32 bit operations 

The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.

The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.

Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15
Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Bas Vermeulen 2017-11-26 22:31:55 +01:00 committed by Paul Fertser
parent bb976e3c38
commit ada631cc5f
3 changed files with 284 additions and 187 deletions
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453
src/target/aarch64.c
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@ -54,7 +54,7 @@ static int aarch64_unset_breakpoint(struct target *target,
static int aarch64_mmu(struct target *target, int *enabled);
static int aarch64_virt2phys(struct target *target,
target_addr_t virt, target_addr_t *phys);
static int aarch64_read_apb_ap_memory(struct target *target,
static int aarch64_read_cpu_memory(struct target *target,
uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
#define foreach_smp_target(pos, head) \
@ -1668,7 +1668,99 @@ static int aarch64_deassert_reset(struct target *target)
return aarch64_init_debug_access(target);
}
static int aarch64_write_apb_ap_memory(struct target *target,
static int aarch64_write_cpu_memory_slow(struct target *target,
uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = &armv8->dpm;
struct arm *arm = &armv8->arm;
int retval;
armv8_reg_current(arm, 1)->dirty = true;
/* change DCC to normal mode if necessary */
if (*dscr & DSCR_MA) {
*dscr &= ~DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
if (retval != ERROR_OK)
return retval;
}
while (count) {
uint32_t data, opcode;
/* write the data to store into DTRRX */
if (size == 1)
data = *buffer;
else if (size == 2)
data = target_buffer_get_u16(target, buffer);
else
data = target_buffer_get_u32(target, buffer);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
if (arm->core_state == ARM_STATE_AARCH64)
retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
else
retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
if (retval != ERROR_OK)
return retval;
if (size == 1)
opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
else if (size == 2)
opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
else
opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
retval = dpm->instr_execute(dpm, opcode);
if (retval != ERROR_OK)
return retval;
/* Advance */
buffer += size;
--count;
}
return ERROR_OK;
}
static int aarch64_write_cpu_memory_fast(struct target *target,
uint32_t count, const uint8_t *buffer, uint32_t *dscr)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm *arm = &armv8->arm;
int retval;
armv8_reg_current(arm, 1)->dirty = true;
/* Step 1.d - Change DCC to memory mode */
*dscr |= DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
if (retval != ERROR_OK)
return retval;
/* Step 2.a - Do the write */
retval = mem_ap_write_buf_noincr(armv8->debug_ap,
buffer, 4, count, armv8->debug_base + CPUV8_DBG_DTRRX);
if (retval != ERROR_OK)
return retval;
/* Step 3.a - Switch DTR mode back to Normal mode */
*dscr &= ~DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static int aarch64_write_cpu_memory(struct target *target,
uint64_t address, uint32_t size,
uint32_t count, const uint8_t *buffer)
{
@ -1677,71 +1769,27 @@ static int aarch64_write_apb_ap_memory(struct target *target,
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = &armv8->dpm;
struct arm *arm = &armv8->arm;
int total_bytes = count * size;
int total_u32;
int start_byte = address & 0x3;
int end_byte = (address + total_bytes) & 0x3;
struct reg *reg;
uint32_t dscr;
uint8_t *tmp_buff = NULL;
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
total_u32 = DIV_ROUND_UP((address & 3) + total_bytes, 4);
/* Mark register R0 as dirty, as it will be used
/* Mark register X0 as dirty, as it will be used
* for transferring the data.
* It will be restored automatically when exiting
* debug mode
*/
reg = armv8_reg_current(arm, 1);
reg->dirty = true;
reg = armv8_reg_current(arm, 0);
reg->dirty = true;
armv8_reg_current(arm, 0)->dirty = true;
/* This algorithm comes from DDI0487A.g, chapter J9.1 */
/* The algorithm only copies 32 bit words, so the buffer
* should be expanded to include the words at either end.
* The first and last words will be read first to avoid
* corruption if needed.
*/
tmp_buff = malloc(total_u32 * 4);
if ((start_byte != 0) && (total_u32 > 1)) {
/* First bytes not aligned - read the 32 bit word to avoid corrupting
* the other bytes in the word.
*/
retval = aarch64_read_apb_ap_memory(target, (address & ~0x3), 4, 1, tmp_buff);
if (retval != ERROR_OK)
goto error_free_buff_w;
}
/* If end of write is not aligned, or the write is less than 4 bytes */
if ((end_byte != 0) ||
((total_u32 == 1) && (total_bytes != 4))) {
/* Read the last word to avoid corruption during 32 bit write */
int mem_offset = (total_u32-1) * 4;
retval = aarch64_read_apb_ap_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
if (retval != ERROR_OK)
goto error_free_buff_w;
}
/* Copy the write buffer over the top of the temporary buffer */
memcpy(&tmp_buff[start_byte], buffer, total_bytes);
/* We now have a 32 bit aligned buffer that can be written */
/* Read DSCR */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
goto error_free_buff_w;
return retval;
/* Set Normal access mode */
dscr = (dscr & ~DSCR_MA);
@ -1753,68 +1801,168 @@ static int aarch64_write_apb_ap_memory(struct target *target,
/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
/* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
retval = dpm->instr_write_data_dcc_64(dpm,
ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address & ~0x3ULL);
ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
} else {
/* Write R0 with value 'address' using write procedure */
/* Step 1.a+b - Write the address for read access into DBGDTRRX */
/* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address & ~0x3ULL);
ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
}
/* Step 1.d - Change DCC to memory mode */
dscr = dscr | DSCR_MA;
retval += mem_ap_write_atomic_u32(armv8->debug_ap,
if (size == 4 && (address % 4) == 0)
retval = aarch64_write_cpu_memory_fast(target, count, buffer, &dscr);
else
retval = aarch64_write_cpu_memory_slow(target, size, count, buffer, &dscr);
if (retval != ERROR_OK) {
/* Unset DTR mode */
mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
dscr &= ~DSCR_MA;
mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
if (retval != ERROR_OK)
goto error_unset_dtr_w;
/* Step 2.a - Do the write */
retval = mem_ap_write_buf_noincr(armv8->debug_ap,
tmp_buff, 4, total_u32, armv8->debug_base + CPUV8_DBG_DTRRX);
if (retval != ERROR_OK)
goto error_unset_dtr_w;
/* Step 3.a - Switch DTR mode back to Normal mode */
dscr = (dscr & ~DSCR_MA);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
if (retval != ERROR_OK)
goto error_unset_dtr_w;
}
/* Check for sticky abort flags in the DSCR */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
goto error_free_buff_w;
return retval;
dpm->dscr = dscr;
if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
/* Abort occurred - clear it and exit */
LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
armv8_dpm_handle_exception(dpm);
goto error_free_buff_w;
}
/* Done */
free(tmp_buff);
return ERROR_OK;
error_unset_dtr_w:
/* Unset DTR mode */
mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
dscr = (dscr & ~DSCR_MA);
mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
error_free_buff_w:
LOG_ERROR("error");
free(tmp_buff);
return ERROR_FAIL;
}
static int aarch64_read_apb_ap_memory(struct target *target,
/* Done */
return ERROR_OK;
}
static int aarch64_read_cpu_memory_slow(struct target *target,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = &armv8->dpm;
struct arm *arm = &armv8->arm;
int retval;
armv8_reg_current(arm, 1)->dirty = true;
/* change DCC to normal mode (if necessary) */
if (*dscr & DSCR_MA) {
*dscr &= DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
if (retval != ERROR_OK)
return retval;
}
while (count) {
uint32_t opcode, data;
if (size == 1)
opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
else if (size == 2)
opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
else
opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
retval = dpm->instr_execute(dpm, opcode);
if (retval != ERROR_OK)
return retval;
if (arm->core_state == ARM_STATE_AARCH64)
retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
else
retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &data);
if (retval != ERROR_OK)
return retval;
if (size == 1)
*buffer = (uint8_t)data;
else if (size == 2)
target_buffer_set_u16(target, buffer, (uint16_t)data);
else
target_buffer_set_u32(target, buffer, data);
/* Advance */
buffer += size;
--count;
}
return ERROR_OK;
}
static int aarch64_read_cpu_memory_fast(struct target *target,
uint32_t count, uint8_t *buffer, uint32_t *dscr)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = &armv8->dpm;
struct arm *arm = &armv8->arm;
int retval;
uint32_t value;
/* Mark X1 as dirty */
armv8_reg_current(arm, 1)->dirty = true;
if (arm->core_state == ARM_STATE_AARCH64) {
/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0));
} else {
/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
}
/* Step 1.e - Change DCC to memory mode */
*dscr |= DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
/* Step 1.f - read DBGDTRTX and discard the value */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &value);
count--;
/* Read the data - Each read of the DTRTX register causes the instruction to be reissued
* Abort flags are sticky, so can be read at end of transactions
*
* This data is read in aligned to 32 bit boundary.
*/
if (count) {
/* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
* increments X0 by 4. */
retval = mem_ap_read_buf_noincr(armv8->debug_ap, buffer, 4, count,
armv8->debug_base + CPUV8_DBG_DTRTX);
if (retval != ERROR_OK)
return retval;
}
/* Step 3.a - set DTR access mode back to Normal mode */
*dscr &= ~DSCR_MA;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
if (retval != ERROR_OK)
return retval;
/* Step 3.b - read DBGDTRTX for the final value */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &value);
if (retval != ERROR_OK)
return retval;
target_buffer_set_u32(target, buffer + count * 4, value);
return retval;
}
static int aarch64_read_cpu_memory(struct target *target,
target_addr_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
@ -1823,32 +1971,22 @@ static int aarch64_read_apb_ap_memory(struct target *target,
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = &armv8->dpm;
struct arm *arm = &armv8->arm;
int total_bytes = count * size;
int total_u32;
int start_byte = address & 0x3;
int end_byte = (address + total_bytes) & 0x3;
struct reg *reg;
uint32_t dscr;
uint8_t *tmp_buff = NULL;
uint8_t *u8buf_ptr;
uint32_t value;
LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
address, size, count);
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
total_u32 = DIV_ROUND_UP((address & 3) + total_bytes, 4);
/* Mark register X0, X1 as dirty, as it will be used
/* Mark register X0 as dirty, as it will be used
* for transferring the data.
* It will be restored automatically when exiting
* debug mode
*/
reg = armv8_reg_current(arm, 1);
reg->dirty = true;
reg = armv8_reg_current(arm, 0);
reg->dirty = true;
armv8_reg_current(arm, 0)->dirty = true;
/* Read DSCR */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
@ -1857,7 +1995,7 @@ static int aarch64_read_apb_ap_memory(struct target *target,
/* This algorithm comes from DDI0487A.g, chapter J9.1 */
/* Set Normal access mode */
dscr = (dscr & ~DSCR_MA);
dscr &= ~DSCR_MA;
retval += mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
@ -1866,83 +2004,34 @@ static int aarch64_read_apb_ap_memory(struct target *target,
/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
/* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
retval += dpm->instr_write_data_dcc_64(dpm,
ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address & ~0x3ULL);
/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
retval += dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0));
/* Step 1.e - Change DCC to memory mode */
dscr = dscr | DSCR_MA;
retval += mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
/* Step 1.f - read DBGDTRTX and discard the value */
retval += mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &value);
ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
} else {
/* Write R0 with value 'address' using write procedure */
/* Step 1.a+b - Write the address for read access into DBGDTRRXint */
/* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
retval += dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address & ~0x3ULL);
/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
retval += dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
/* Step 1.e - Change DCC to memory mode */
dscr = dscr | DSCR_MA;
retval += mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
/* Step 1.f - read DBGDTRTX and discard the value */
retval += mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &value);
ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
}
if (retval != ERROR_OK)
goto error_unset_dtr_r;
/* Optimize the read as much as we can, either way we read in a single pass */
if ((start_byte) || (end_byte)) {
/* The algorithm only copies 32 bit words, so the buffer
* should be expanded to include the words at either end.
* The first and last words will be read into a temp buffer
* to avoid corruption
*/
tmp_buff = malloc(total_u32 * 4);
if (!tmp_buff)
goto error_unset_dtr_r;
if (size == 4 && (address % 4) == 0)
retval = aarch64_read_cpu_memory_fast(target, count, buffer, &dscr);
else
retval = aarch64_read_cpu_memory_slow(target, size, count, buffer, &dscr);
/* use the tmp buffer to read the entire data */
u8buf_ptr = tmp_buff;
} else
/* address and read length are aligned so read directly into the passed buffer */
u8buf_ptr = buffer;
/* Read the data - Each read of the DTRTX register causes the instruction to be reissued
* Abort flags are sticky, so can be read at end of transactions
*
* This data is read in aligned to 32 bit boundary.
*/
/* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
* increments X0 by 4. */
retval = mem_ap_read_buf_noincr(armv8->debug_ap, u8buf_ptr, 4, total_u32-1,
armv8->debug_base + CPUV8_DBG_DTRTX);
if (retval != ERROR_OK)
goto error_unset_dtr_r;
/* Step 3.a - set DTR access mode back to Normal mode */
dscr = (dscr & ~DSCR_MA);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
if (dscr & DSCR_MA) {
dscr &= ~DSCR_MA;
mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
if (retval != ERROR_OK)
goto error_free_buff_r;
}
/* Step 3.b - read DBGDTRTX for the final value */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRTX, &value);
memcpy(u8buf_ptr + (total_u32-1) * 4, &value, 4);
if (retval != ERROR_OK)
return retval;
/* Check for sticky abort flags in the DSCR */
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
goto error_free_buff_r;
return retval;
dpm->dscr = dscr;
@ -1950,29 +2039,11 @@ static int aarch64_read_apb_ap_memory(struct target *target,
/* Abort occurred - clear it and exit */
LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
armv8_dpm_handle_exception(dpm);
goto error_free_buff_r;
}
/* check if we need to copy aligned data by applying any shift necessary */
if (tmp_buff) {
memcpy(buffer, tmp_buff + start_byte, total_bytes);
free(tmp_buff);
return ERROR_FAIL;
}
/* Done */
return ERROR_OK;
error_unset_dtr_r:
/* Unset DTR mode */
mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
dscr = (dscr & ~DSCR_MA);
mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, dscr);
error_free_buff_r:
LOG_ERROR("error");
free(tmp_buff);
return ERROR_FAIL;
}
static int aarch64_read_phys_memory(struct target *target,
@ -1986,7 +2057,7 @@ static int aarch64_read_phys_memory(struct target *target,
retval = aarch64_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
retval = aarch64_read_apb_ap_memory(target, address, size, count, buffer);
retval = aarch64_read_cpu_memory(target, address, size, count, buffer);
}
return retval;
}
@ -2008,7 +2079,7 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
if (retval != ERROR_OK)
return retval;
}
return aarch64_read_apb_ap_memory(target, address, size, count, buffer);
return aarch64_read_cpu_memory(target, address, size, count, buffer);
}
static int aarch64_write_phys_memory(struct target *target,
@ -2022,7 +2093,7 @@ static int aarch64_write_phys_memory(struct target *target,
retval = aarch64_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
return aarch64_write_cpu_memory(target, address, size, count, buffer);
}
return retval;
@ -2045,7 +2116,7 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
if (retval != ERROR_OK)
return retval;
}
return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
return aarch64_write_cpu_memory(target, address, size, count, buffer);
}
static int aarch64_handle_target_request(void *priv)

12
src/target/armv8_opcodes.c
View File

@ -42,6 +42,12 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
[ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
[ARMV8_OPC_HLT] = ARMV8_HLT(11),
[ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0),
[ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0),
[ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP(1, 0),
[ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP(1, 0),
[ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0),
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
@ -63,6 +69,12 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
[ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
[ARMV8_OPC_HLT] = ARMV8_HLT_A1(11),
[ARMV8_OPC_LDRB_IP] = ARMV4_5_LDRB_IP(1, 0),
[ARMV8_OPC_LDRH_IP] = ARMV4_5_LDRH_IP(1, 0),
[ARMV8_OPC_LDRW_IP] = ARMV4_5_LDRW_IP(1, 0),
[ARMV8_OPC_STRB_IP] = ARMV4_5_STRB_IP(1, 0),
[ARMV8_OPC_STRH_IP] = ARMV4_5_STRH_IP(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV4_5_STRW_IP(1, 0),
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)

14
src/target/armv8_opcodes.h
View File

@ -159,6 +159,14 @@
#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
enum armv8_opcode {
@ -180,6 +188,12 @@ enum armv8_opcode {
ARMV8_OPC_DCCIVAC,
ARMV8_OPC_ICIVAU,
ARMV8_OPC_HLT,
ARMV8_OPC_STRB_IP,
ARMV8_OPC_STRH_IP,
ARMV8_OPC_STRW_IP,
ARMV8_OPC_LDRB_IP,
ARMV8_OPC_LDRH_IP,
ARMV8_OPC_LDRW_IP,
ARMV8_OPC_NUM,
};