interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: remove 'armv4_5_common_s' migration #define 

Finish migrating from the old symbol to the new one.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-11-22 10:19:58 -08:00
parent 5416c525d4
commit ab5ac33fd4
12 changed files with 53 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/target/arm720t.c
View File

@ -225,7 +225,7 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx,
static int arm720t_arch_state(struct target *target) static int arm720t_arch_state(struct target *target)
{ {
struct arm720t_common *arm720t = target_to_arm720(target); struct arm720t_common *arm720t = target_to_arm720(target);
struct armv4_5_common_s *armv4_5; struct arm *armv4_5;
static const char *state[] = static const char *state[] =
{ {
@ -307,7 +307,7 @@ static int arm720t_soft_reset_halt(struct target *target)
struct arm720t_common *arm720t = target_to_arm720(target); struct arm720t_common *arm720t = target_to_arm720(target);
struct reg *dbg_stat = &arm720t->arm7_9_common struct reg *dbg_stat = &arm720t->arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT]; .eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm720t->arm7_9_common struct arm *armv4_5 = &arm720t->arm7_9_common
.armv4_5_common; .armv4_5_common;
if ((retval = target_halt(target)) != ERROR_OK) if ((retval = target_halt(target)) != ERROR_OK)

22
src/target/arm7_9_common.c
View File

@ -1160,7 +1160,7 @@ int arm7_9_clear_halt(struct target *target)
int arm7_9_soft_reset_halt(struct target *target) int arm7_9_soft_reset_halt(struct target *target)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i; int i;
@ -1338,7 +1338,7 @@ static int arm7_9_debug_entry(struct target *target)
uint32_t cpsr, cpsr_mask = 0; uint32_t cpsr, cpsr_mask = 0;
int retval; int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@ -1492,7 +1492,7 @@ int arm7_9_full_context(struct target *target)
int i; int i;
int retval; int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-"); LOG_DEBUG("-");
@ -1586,7 +1586,7 @@ int arm7_9_full_context(struct target *target)
int arm7_9_restore_context(struct target *target) int arm7_9_restore_context(struct target *target)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg; struct reg *reg;
struct arm_reg *reg_arch_info; struct arm_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode; enum armv4_5_mode current_mode = armv4_5->core_mode;
@ -1797,7 +1797,7 @@ void arm7_9_enable_breakpoints(struct target *target)
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints; struct breakpoint *breakpoint = target->breakpoints;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK; int err, retval = ERROR_OK;
@ -1957,7 +1957,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc; uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
@ -2009,7 +2009,7 @@ void arm7_9_disable_eice_step(struct target *target)
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = NULL; struct breakpoint *breakpoint = NULL;
int err, retval; int err, retval;
@ -2107,7 +2107,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
int retval; int retval;
struct arm_reg *areg = r->arch_info; struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode)) if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL; return ERROR_FAIL;
@ -2169,7 +2169,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
uint32_t reg[16]; uint32_t reg[16];
struct arm_reg *areg = r->arch_info; struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode)) if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL; return ERROR_FAIL;
@ -2227,7 +2227,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16]; uint32_t reg[16];
uint32_t num_accesses = 0; uint32_t num_accesses = 0;
int thisrun_accesses; int thisrun_accesses;
@ -2404,7 +2404,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16]; uint32_t reg[16];

4
src/target/arm7tdmi.c
View File

@ -581,7 +581,7 @@ static void arm7tdmi_branch_resume(struct target *target)
static void arm7tdmi_branch_resume_thumb(struct target *target) static void arm7tdmi_branch_resume_thumb(struct target *target)
{ {
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -641,7 +641,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
static void arm7tdmi_build_reg_cache(struct target *target) static void arm7tdmi_build_reg_cache(struct target *target)
{ {
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
} }

12
src/target/arm920t.c
View File

@ -212,7 +212,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
static int arm920t_read_cp15_interpreted(struct target *target, static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value) uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t* regs_p[1]; uint32_t* regs_p[1];
uint32_t regs[2]; uint32_t regs[2];
uint32_t cp15c15 = 0x0; uint32_t cp15c15 = 0x0;
@ -258,7 +258,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t value, uint32_t address) uint32_t cp15_opcode, uint32_t value, uint32_t address)
{ {
uint32_t cp15c15 = 0x0; uint32_t cp15c15 = 0x0;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t regs[2]; uint32_t regs[2];
/* load value, address into R0, R1 */ /* load value, address into R0, R1 */
@ -436,7 +436,7 @@ int arm920t_arch_state(struct target *target)
}; };
struct arm920t_common *arm920t = target_to_arm920(target); struct arm920t_common *arm920t = target_to_arm920(target);
struct armv4_5_common_s *armv4_5; struct arm *armv4_5;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC) if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{ {
@ -555,7 +555,7 @@ int arm920t_soft_reset_halt(struct target *target)
int retval = ERROR_OK; int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target); struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK) if ((retval = target_halt(target)) != ERROR_OK)
@ -668,7 +668,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target); struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15; uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16]; uint32_t regs[16];
@ -914,7 +914,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target); struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15; uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16]; uint32_t regs[16];

4
src/target/arm926ejs.c
View File

@ -494,7 +494,7 @@ int arm926ejs_arch_state(struct target *target)
}; };
struct arm926ejs_common *arm926ejs = target_to_arm926(target); struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct armv4_5_common_s *armv4_5; struct arm *armv4_5;
if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
{ {
@ -524,7 +524,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
int retval = ERROR_OK; int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target); struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK) if ((retval = target_halt(target)) != ERROR_OK)

4
src/target/arm9tdmi.c
View File

@ -664,7 +664,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target)
LOG_DEBUG("-"); LOG_DEBUG("-");
struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -751,7 +751,7 @@ void arm9tdmi_disable_single_step(struct target *target)
static void arm9tdmi_build_reg_cache(struct target *target) static void arm9tdmi_build_reg_cache(struct target *target)
{ {
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
} }

2
src/target/arm_simulator.c
View File

@ -850,7 +850,7 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
struct arm_sim_interface sim; struct arm_sim_interface sim;
sim.user_data = armv4_5; sim.user_data = armv4_5;

16
src/target/armv4_5.c
View File

@ -487,7 +487,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{ {
struct arm_reg *armv4_5 = reg->arch_info; struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target; struct target *target = armv4_5->target;
struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target); struct arm *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32); uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
@ -579,7 +579,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
int armv4_5_arch_state(struct target *target) int armv4_5_arch_state(struct target *target)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
@ -603,7 +603,7 @@ int armv4_5_arch_state(struct target *target)
COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_reg_command)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs; unsigned num_regs;
struct reg *regs; struct reg *regs;
@ -690,7 +690,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
COMMAND_HANDLER(handle_armv4_5_core_state_command) COMMAND_HANDLER(handle_armv4_5_core_state_command)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
if (!is_arm(armv4_5)) if (!is_arm(armv4_5))
{ {
@ -810,7 +810,7 @@ int armv4_5_register_commands(struct command_context *cmd_ctx)
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
int i; int i;
if (!is_arm_mode(armv4_5->core_mode)) if (!is_arm_mode(armv4_5->core_mode))
@ -835,7 +835,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{ {
int retval; int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{ {
@ -866,7 +866,7 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state; enum armv4_5_state core_state = armv4_5->core_state;
uint32_t context[17]; uint32_t context[17];
@ -1217,7 +1217,7 @@ int arm_blank_check_memory(struct target *target,
static int arm_full_context(struct target *target) static int arm_full_context(struct target *target)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs = armv4_5->core_cache->num_regs; unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list; struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK; int retval = ERROR_OK;

3
src/target/armv4_5.h
View File

@ -67,9 +67,6 @@ enum { ARMV4_5_CPSR = 31, };
#define ARMV4_5_COMMON_MAGIC 0x0A450A45 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
/* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
#define armv4_5_common_s arm
/** /**
* Represents a generic ARM core, with standard application registers. * Represents a generic ARM core, with standard application registers.
* *

2
src/target/armv7a.c
View File

@ -59,7 +59,7 @@ int armv7a_arch_state(struct target *target)
}; };
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; struct arm *armv4_5 = &armv7a->armv4_5_common;
if (armv7a->common_magic != ARMV7_COMMON_MAGIC) if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
{ {

16
src/target/cortex_a8.c
View File

@ -457,7 +457,7 @@ static int cortex_a8_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution) uint32_t address, int handle_breakpoints, int debug_execution)
{ {
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info; struct swjdp_common *swjdp = &armv7a->swjdp_info;
// struct breakpoint *breakpoint = NULL; // struct breakpoint *breakpoint = NULL;
@ -587,7 +587,7 @@ static int cortex_a8_debug_entry(struct target *target)
struct working_area *regfile_working_area = NULL; struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info; struct swjdp_common *swjdp = &armv7a->swjdp_info;
struct reg *reg; struct reg *reg;
@ -743,7 +743,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
int handle_breakpoints) int handle_breakpoints)
{ {
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; struct arm *armv4_5 = &armv7a->armv4_5_common;
struct breakpoint *breakpoint = NULL; struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint; struct breakpoint stepbreakpoint;
@ -915,7 +915,7 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t * value) armv4_5_mode_t mode, uint32_t * value)
{ {
int retval; int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
if ((num <= ARM_CPSR)) if ((num <= ARM_CPSR))
{ {
@ -953,7 +953,7 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
{ {
int retval; int retval;
// uint32_t reg; // uint32_t reg;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
#ifdef ARMV7_GDB_HACKS #ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us /* If the LR register is being modified, make sure it will put us
@ -998,7 +998,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
{ {
uint32_t value; uint32_t value;
int retval; int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
struct reg *cpsr_r = NULL; struct reg *cpsr_r = NULL;
uint32_t cpsr = 0; uint32_t cpsr = 0;
unsigned cookie = num; unsigned cookie = num;
@ -1053,7 +1053,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
int num, enum armv4_5_mode mode, uint32_t value) int num, enum armv4_5_mode mode, uint32_t value)
{ {
int retval; int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
struct reg *cpsr_r = NULL; struct reg *cpsr_r = NULL;
uint32_t cpsr = 0; uint32_t cpsr = 0;
unsigned cookie = num; unsigned cookie = num;
@ -1584,7 +1584,7 @@ static int cortex_a8_examine(struct target *target)
static void cortex_a8_build_reg_cache(struct target *target) static void cortex_a8_build_reg_cache(struct target *target)
{ {
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
armv4_5->core_type = ARM_MODE_MON; armv4_5->core_type = ARM_MODE_MON;

20
src/target/xscale.c
View File

@ -833,7 +833,7 @@ static int xscale_update_vectors(struct target *target)
static int xscale_arch_state(struct target *target) static int xscale_arch_state(struct target *target)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
static const char *state[] = static const char *state[] =
{ {
@ -911,7 +911,7 @@ static int xscale_poll(struct target *target)
static int xscale_debug_entry(struct target *target) static int xscale_debug_entry(struct target *target)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t pc; uint32_t pc;
uint32_t buffer[10]; uint32_t buffer[10];
int i; int i;
@ -1179,7 +1179,7 @@ static int xscale_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution) uint32_t address, int handle_breakpoints, int debug_execution)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints; struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc; uint32_t current_pc;
int retval; int retval;
@ -1335,7 +1335,7 @@ static int xscale_step_inner(struct target *target, int current,
uint32_t address, int handle_breakpoints) uint32_t address, int handle_breakpoints)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t next_pc; uint32_t next_pc;
int retval; int retval;
int i; int i;
@ -1416,7 +1416,7 @@ static int xscale_step_inner(struct target *target, int current,
static int xscale_step(struct target *target, int current, static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints) uint32_t address, int handle_breakpoints)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
struct breakpoint *breakpoint = target->breakpoints; struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc; uint32_t current_pc;
@ -1661,7 +1661,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
static int xscale_full_context(struct target *target) static int xscale_full_context(struct target *target)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t *buffer; uint32_t *buffer;
@ -1737,7 +1737,7 @@ static int xscale_full_context(struct target *target)
static int xscale_restore_context(struct target *target) static int xscale_restore_context(struct target *target)
{ {
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
int i, j; int i, j;
@ -2470,7 +2470,7 @@ static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
static int xscale_read_trace(struct target *target) static int xscale_read_trace(struct target *target)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
struct xscale_trace_data **trace_data_p; struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler /* 258 words from debug handler
@ -2821,7 +2821,7 @@ static const struct reg_arch_type xscale_reg_type = {
static void xscale_build_reg_cache(struct target *target) static void xscale_build_reg_cache(struct target *target)
{ {
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info)); struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i; int i;
@ -3271,7 +3271,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target); struct xscale_common *xscale = target_to_xscale(target);
struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t dcsr_value; uint32_t dcsr_value;
int retval; int retval;