From a740a06bbc9d4f74f60c32384af48f5d0a4a2383 Mon Sep 17 00:00:00 2001
From: Greg Savin <43152568+SiFiveGregS@users.noreply.github.com>
Date: Mon, 8 Apr 2019 11:14:30 -0700
Subject: [PATCH] A couple fixes.

---
 src/target/riscv/riscv.c                  | 2 +-
 tcl/board/sifive-e31arty-onboard-ftdi.cfg | 7 +------
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 749b533fb..9415b8d4a 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -206,7 +206,7 @@ struct scan_field _bscan_tunneled_select_dmi[] = {
 		}
 };
 struct scan_field *bscan_tunneled_select_dmi = _bscan_tunneled_select_dmi;
-uint32_t bscan_tunneled_select_dmi_num_fields = sizeof(bscan_tunneled_select_dmi)/sizeof(bscan_tunneled_select_dmi[0]);
+uint32_t bscan_tunneled_select_dmi_num_fields = DIM(_bscan_tunneled_select_dmi);
 #endif
 
 struct trigger {
diff --git a/tcl/board/sifive-e31arty-onboard-ftdi.cfg b/tcl/board/sifive-e31arty-onboard-ftdi.cfg
index cd7f391ba..db1bfdbe1 100644
--- a/tcl/board/sifive-e31arty-onboard-ftdi.cfg
+++ b/tcl/board/sifive-e31arty-onboard-ftdi.cfg
@@ -6,15 +6,10 @@
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 6; # -expected-id 0x0362d093
 
-# Arrange for bscan tunneling mode to become active after the JTAG chain is verified (or has been reset but even if the full verification sequence wasn't perfect)
-jtag configure $_CHIPNAME.cpu -event setup {
-  ftdi_bscan_mode on
-}
-
 set _TARGETNAME $_CHIPNAME.cpu
 
 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 -bscan-tunnel-ir-width 5
 
 # Uncomment if hardware has flash
 # flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000