Initial ETM cleanups. Most of these are cosmetic:
- Add a header comment - Line up the ETM context struct, pack it a bit - Remove unused context_id (this doesn't support ETMv2 yet) - Make most functions static - Remove unused string table and other needless lines of code - Correct "tracemode" helptext Also provide and use an etm_reg_lookup() to find entries in the ETM register cache. This will help cope with corrected contents of that cache, which doesn't include entires for non-existent registers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2750 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
dbrownell
parent
7393fcfc90
commit
a6d858ebcd
147
src/target/etm.c
147
src/target/etm.c
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@ -28,20 +28,28 @@
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#include "arm_disassembler.h"
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/* ETM register access functionality
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/*
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* ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
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*
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* ETM modules collect instruction and/or data trace information, compress
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* it, and transfer it to a debugging host through either a (buffered) trace
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* port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
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*
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* There are several generations of these modules. Original versions have
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* JTAG access through a dedicated scan chain. Recent versions have added
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* access via coprocessor instructions, memory addressing, and the ARM Debug
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* Interface v5 (ADIv5); and phased out direct JTAG access.
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*
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* This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
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* most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
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* implying non-JTAG connectivity options.
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*
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* Relevant documentation includes:
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* ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
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* ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
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* ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
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*/
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#if 0
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static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
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{
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{"R", 1},
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{"W", 1},
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{"reserved", 26},
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{"version", 4}
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};
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#endif
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static int etm_reg_arch_info[] =
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{
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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@ -196,10 +204,38 @@ static char* etm_reg_list[] =
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static int etm_reg_arch_type = -1;
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static int etm_get_reg(reg_t *reg);
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static int etm_read_reg_w_check(reg_t *reg,
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uint8_t* check_value, uint8_t* check_mask);
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static int etm_register_user_commands(struct command_context_s *cmd_ctx);
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static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
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static int etm_write_reg(reg_t *reg, uint32_t value);
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static command_t *etm_cmd = NULL;
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static command_t *etm_cmd;
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reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
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/* Look up register by ID ... most ETM instances only
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* support a subset of the possible registers.
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*/
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static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
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{
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reg_cache_t *cache = etm_ctx->reg_cache;
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int i;
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for (i = 0; i < cache->num_regs; i++) {
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struct etm_reg_s *reg = cache->reg_list[i].arch_info;
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if (reg->addr == (int) id)
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return &cache->reg_list[i];
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}
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/* caller asking for nonexistent register is a bug! */
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/* REVISIT say which of the N targets was involved */
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LOG_ERROR("ETM: register 0x%02x not available", id);
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return NULL;
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}
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reg_cache_t *etm_build_reg_cache(target_t *target,
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arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
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{
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reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = NULL;
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@ -226,10 +262,6 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
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{
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reg_list[i].name = etm_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].bitfield_desc = NULL;
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reg_list[i].num_bitfields = 0;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].arch_type = etm_reg_arch_type;
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@ -264,6 +296,16 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
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return reg_cache;
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}
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static int etm_read_reg(reg_t *reg)
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{
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return etm_read_reg_w_check(reg, NULL, NULL);
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}
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static int etm_store_reg(reg_t *reg)
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{
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return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
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}
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int etm_setup(target_t *target)
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{
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int retval;
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@ -271,7 +313,11 @@ int etm_setup(target_t *target)
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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etm_context_t *etm_ctx = arm7_9->etm_ctx;
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reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
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reg_t *etm_ctrl_reg;
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etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
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if (!etm_ctrl_reg)
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return ERROR_OK;
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/* initialize some ETM control register settings */
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etm_get_reg(etm_ctrl_reg);
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@ -299,7 +345,7 @@ int etm_setup(target_t *target)
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return ERROR_OK;
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}
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int etm_get_reg(reg_t *reg)
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static int etm_get_reg(reg_t *reg)
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{
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int retval;
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@ -318,7 +364,8 @@ int etm_get_reg(reg_t *reg)
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return ERROR_OK;
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}
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int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
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static int etm_read_reg_w_check(reg_t *reg,
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uint8_t* check_value, uint8_t* check_mask)
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{
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etm_reg_t *etm_reg = reg->arch_info;
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uint8_t reg_addr = etm_reg->addr & 0x7f;
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@ -367,12 +414,7 @@ int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
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return ERROR_OK;
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}
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int etm_read_reg(reg_t *reg)
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{
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return etm_read_reg_w_check(reg, NULL, NULL);
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}
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int etm_set_reg(reg_t *reg, uint32_t value)
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static int etm_set_reg(reg_t *reg, uint32_t value)
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{
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int retval;
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@ -389,7 +431,7 @@ int etm_set_reg(reg_t *reg, uint32_t value)
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return ERROR_OK;
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}
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int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
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static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
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{
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int retval;
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@ -403,7 +445,7 @@ int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
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return ERROR_OK;
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}
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int etm_write_reg(reg_t *reg, uint32_t value)
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static int etm_write_reg(reg_t *reg, uint32_t value)
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{
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etm_reg_t *etm_reg = reg->arch_info;
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uint8_t reg_addr = etm_reg->addr & 0x7f;
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@ -441,10 +483,6 @@ int etm_write_reg(reg_t *reg, uint32_t value)
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return ERROR_OK;
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}
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int etm_store_reg(reg_t *reg)
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{
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return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
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}
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/* ETM trace analysis functionality
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*
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@ -464,18 +502,6 @@ static etm_capture_driver_t *etm_capture_drivers[] =
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NULL
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};
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char *etmv1v1_branch_reason_strings[] =
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{
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"normal PC change",
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"tracing enabled",
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"trace restarted after overflow",
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"exit from debug",
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"periodic synchronization",
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"reserved",
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"reserved",
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"reserved",
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};
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static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
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{
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int i;
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@ -1172,7 +1198,11 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
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/* only update ETM_CTRL register if tracemode changed */
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if (arm7_9->etm_ctx->tracemode != tracemode)
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{
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reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
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reg_t *etm_ctrl_reg;
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etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
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if (!etm_ctrl_reg)
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return ERROR_OK;
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etm_get_reg(etm_ctrl_reg);
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@ -1319,7 +1349,6 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm
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etm_ctx->last_branch_reason = 0x0;
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etm_ctx->last_ptr = 0x0;
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etm_ctx->ptr_ok = 0x0;
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etm_ctx->context_id = 0x0;
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etm_ctx->last_instruction = 0;
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arm7_9->etm_ctx = etm_ctx;
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@ -1327,7 +1356,8 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm
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return etm_register_user_commands(cmd_ctx);
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}
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int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int handle_etm_info_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target;
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armv4_5_common_t *armv4_5;
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@ -1351,8 +1381,12 @@ int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char *
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return ERROR_OK;
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}
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etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
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etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
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etm_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CONFIG);
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if (!etm_config_reg)
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return ERROR_OK;
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etm_sys_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_SYS_CONFIG);
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if (!etm_sys_config_reg)
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return ERROR_OK;
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etm_get_reg(etm_config_reg);
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command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
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@ -1732,7 +1766,10 @@ static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd
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}
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arm7_9->etm_ctx->trace_depth = 0;
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etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
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etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
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if (!etm_ctrl_reg)
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return ERROR_OK;
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etm_get_reg(etm_ctrl_reg);
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/* Clear programming bit (10), set port selection bit (11) */
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@ -1768,7 +1805,10 @@ static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd,
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return ERROR_OK;
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}
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etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
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etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
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if (!etm_ctrl_reg)
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return ERROR_OK;
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etm_get_reg(etm_ctrl_reg);
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/* Set programming bit (10), clear port selection bit (11) */
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@ -1835,10 +1875,11 @@ int etm_register_commands(struct command_context_s *cmd_ctx)
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return ERROR_OK;
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}
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int etm_register_user_commands(struct command_context_s *cmd_ctx)
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static int etm_register_user_commands(struct command_context_s *cmd_ctx)
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{
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register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
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COMMAND_EXEC, "configure trace mode <none | data | address | all> "
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COMMAND_EXEC, "configure/display trace mode: "
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"<none | data | address | all> "
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"<context_id_bits> <cycle_accurate> <branch_output>");
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register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
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@ -143,25 +143,24 @@ typedef struct etm_context_s
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reg_cache_t *reg_cache; /* ETM register cache */
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etm_capture_driver_t *capture_driver; /* driver used to access ETM data */
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void *capture_driver_priv; /* capture driver private data */
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uint32_t trigger_percent; /* percent of trace buffer to be filled after the trigger */
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uint32_t trigger_percent; /* how much trace buffer to fill after trigger */
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trace_status_t capture_status; /* current state of capture run */
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etmv1_trace_data_t *trace_data; /* trace data */
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uint32_t trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */
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uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
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etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
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etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */
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armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
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etmv1_tracemode_t tracemode; /* type of info trace contains */
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armv4_5_state_t core_state; /* current core state */
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struct image_s *image; /* source for target opcodes */
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uint32_t pipe_index; /* current trace cycle */
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uint32_t data_index; /* cycle holding next data packet */
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int data_half; /* port half on a 16 bit port */
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bool data_half; /* port half on a 16 bit port */
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bool pc_ok; /* full PC has been acquired */
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bool ptr_ok; /* whether last_ptr is valid */
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uint32_t current_pc; /* current program counter */
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uint32_t pc_ok; /* full PC has been acquired */
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uint32_t last_branch; /* last branch address output */
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uint32_t last_branch_reason; /* branch reason code for the last branch encountered */
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uint32_t last_branch_reason; /* type of last branch encountered */
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uint32_t last_ptr; /* address of the last data access */
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uint32_t ptr_ok; /* whether last_ptr is valid */
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uint32_t context_id; /* context ID of the code being traced */
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uint32_t last_instruction; /* index of last instruction executed (to calculate cycle timings) */
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uint32_t last_instruction; /* index of last executed (to calc timings) */
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} etm_context_t;
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/* PIPESTAT values */
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@ -190,20 +189,10 @@ typedef enum
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BR_RSVD7 = 0x7, /* reserved */
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} etmv1_branch_reason_t;
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extern char *etmv1v1_branch_reason_strings[];
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extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
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extern int etm_read_reg(reg_t *reg);
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extern int etm_write_reg(reg_t *reg, uint32_t value);
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extern int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask);
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extern int etm_store_reg(reg_t *reg);
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extern int etm_set_reg(reg_t *reg, uint32_t value);
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extern int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
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extern int etm_setup(target_t *target);
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int etm_register_commands(struct command_context_s *cmd_ctx);
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int etm_register_user_commands(struct command_context_s *cmd_ctx);
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extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
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#define ERROR_ETM_INVALID_DRIVER (-1300)
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#define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
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