Support for sam3n0a sam3n0b sam3n00a sam3n00b
Change-Id: I70a04f5f9b0b20d42a677ea8781130e44be758d3 Signed-off-by: Stefan Arnold <sarnold@sh-sw.de> Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2042 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
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@ -1518,6 +1518,143 @@ static const struct sam3_chip_details all_sam3_details[] = {
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},
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},
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{
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.chipid_cidr = 0x29480360,
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.name = "at91sam3n0b",
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.total_flash_size = 32 * 1024,
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.total_sram_size = 8 * 1024,
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.n_gpnvms = 3,
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.n_banks = 1,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_N,
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.controller_address = 0x400e0A00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.present = 1,
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.size_bytes = 32 * 1024,
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.nsectors = 2,
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.sector_size = 16384,
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.page_size = 256,
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},
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/* .bank[1] = { */
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x29380360,
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.name = "at91sam3n0a",
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.total_flash_size = 32 * 1024,
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.total_sram_size = 8 * 1024,
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.n_gpnvms = 3,
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.n_banks = 1,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_N,
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.controller_address = 0x400e0A00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.present = 1,
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.size_bytes = 32 * 1024,
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.nsectors = 2,
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.sector_size = 16384,
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.page_size = 256,
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},
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/* .bank[1] = { */
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x29450260,
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.name = "at91sam3n00b",
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.total_flash_size = 16 * 1024,
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.total_sram_size = 4 * 1024,
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.n_gpnvms = 3,
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.n_banks = 1,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_N,
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.controller_address = 0x400e0A00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.present = 1,
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.size_bytes = 16 * 1024,
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.nsectors = 1,
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.sector_size = 16384,
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.page_size = 256,
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},
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/* .bank[1] = { */
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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{
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.chipid_cidr = 0x29350260,
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.name = "at91sam3n00a",
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.total_flash_size = 16 * 1024,
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.total_sram_size = 4 * 1024,
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.n_gpnvms = 3,
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.n_banks = 1,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_N,
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.controller_address = 0x400e0A00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.present = 1,
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.size_bytes = 16 * 1024,
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.nsectors = 1,
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.sector_size = 16384,
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.page_size = 256,
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},
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/* .bank[1] = { */
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/* Start at91sam3a series*/
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/* System boots at address 0x0 */
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/* gpnvm[1] = selects boot code */
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@ -2993,7 +3130,7 @@ static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
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pDetails = all_sam3_details;
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while (pDetails->name) {
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/* Compare cidr without version bits */
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if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
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if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
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break;
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else
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pDetails++;
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