- remove build warnings from mips_m4k.c and arm11.c
- reformat whitespace arm11.c[ch] - add missing svn props from mips32_dmaacc.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@1032 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
parent
30e5bff4b8
commit
a5806d21d2
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@ -32,12 +32,12 @@
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* DCRDR[23:16] is used for by host for status
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* DCRDR[31:24] is used for by host for write buffer */
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#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
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#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
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#define TARGET_REQ_TRACEMSG 0x00
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#define TARGET_REQ_DEBUGMSG_ASCII 0x01
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#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
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#define TARGET_REQ_DEBUGCHAR 0x02
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#define TARGET_REQ_TRACEMSG 0x00
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#define TARGET_REQ_DEBUGMSG_ASCII 0x01
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#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
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#define TARGET_REQ_DEBUGCHAR 0x02
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#define BUSY 1
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1581
src/target/arm11.c
1581
src/target/arm11.c
File diff suppressed because it is too large
Load Diff
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@ -28,12 +28,10 @@
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#include "arm_jtag.h"
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#include <stdbool.h>
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#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
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#define NEW(type, variable, items) \
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type * variable = calloc(1, sizeof(type) * items)
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type * variable = calloc(1, sizeof(type) * items)
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/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
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@ -43,7 +41,6 @@
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#define ZU "%Iu"
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#endif
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#define ARM11_REGCACHE_MODEREGS 0
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#define ARM11_REGCACHE_FREGS 0
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@ -51,63 +48,60 @@
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23 * ARM11_REGCACHE_MODEREGS + \
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9 * ARM11_REGCACHE_FREGS)
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typedef struct arm11_register_history_s
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{
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u32 value;
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u8 valid;
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u32 value;
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u8 valid;
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}arm11_register_history_t;
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enum arm11_debug_version
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{
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ARM11_DEBUG_V6 = 0x01,
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ARM11_DEBUG_V61 = 0x02,
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ARM11_DEBUG_V7 = 0x03,
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ARM11_DEBUG_V7_CP14 = 0x04,
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ARM11_DEBUG_V6 = 0x01,
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ARM11_DEBUG_V61 = 0x02,
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ARM11_DEBUG_V7 = 0x03,
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ARM11_DEBUG_V7_CP14 = 0x04,
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};
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typedef struct arm11_common_s
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{
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target_t * target;
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target_t * target;
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arm_jtag_t jtag_info;
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arm_jtag_t jtag_info;
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/** \name Processor type detection */
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/*@{*/
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/** \name Processor type detection */
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/*@{*/
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u32 device_id; /**< IDCODE readout */
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u32 didr; /**< DIDR readout (debug capabilities) */
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u8 implementor; /**< DIDR Implementor readout */
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u32 device_id; /**< IDCODE readout */
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u32 didr; /**< DIDR readout (debug capabilities) */
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u8 implementor; /**< DIDR Implementor readout */
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size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
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size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
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size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
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size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
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enum arm11_debug_version
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debug_version; /**< ARM debug architecture from DIDR */
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/*@}*/
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enum arm11_debug_version
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debug_version; /**< ARM debug architecture from DIDR */
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/*@}*/
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u32 last_dscr; /**< Last retrieved DSCR value;
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* Can be used to detect changes */
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u32 last_dscr; /**< Last retrieved DSCR value;
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* Can be used to detect changes */
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bool trst_active;
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bool halt_requested;
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bool simulate_reset_on_next_halt;
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bool trst_active;
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bool halt_requested;
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bool simulate_reset_on_next_halt;
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/** \name Shadow registers to save processor state */
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/*@{*/
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/** \name Shadow registers to save processor state */
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/*@{*/
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reg_t * reg_list; /**< target register list */
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u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
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reg_t * reg_list; /**< target register list */
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u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
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/*@}*/
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/*@}*/
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arm11_register_history_t
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arm11_register_history_t
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reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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// GA
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reg_cache_t *core_cache;
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@ -121,65 +115,60 @@ typedef struct arm11_common_s
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*/
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enum arm11_instructions
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{
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ARM11_EXTEST = 0x00,
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ARM11_SCAN_N = 0x02,
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ARM11_RESTART = 0x04,
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ARM11_HALT = 0x08,
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ARM11_INTEST = 0x0C,
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ARM11_ITRSEL = 0x1D,
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ARM11_IDCODE = 0x1E,
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ARM11_BYPASS = 0x1F,
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ARM11_EXTEST = 0x00,
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ARM11_SCAN_N = 0x02,
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ARM11_RESTART = 0x04,
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ARM11_HALT = 0x08,
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ARM11_INTEST = 0x0C,
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ARM11_ITRSEL = 0x1D,
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ARM11_IDCODE = 0x1E,
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ARM11_BYPASS = 0x1F,
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};
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enum arm11_dscr
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{
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ARM11_DSCR_CORE_HALTED = 1 << 0,
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ARM11_DSCR_CORE_RESTARTED = 1 << 1,
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ARM11_DSCR_CORE_HALTED = 1 << 0,
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ARM11_DSCR_CORE_RESTARTED = 1 << 1,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
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ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
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ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
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ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
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ARM11_DSCR_MODE_SELECT = 1 << 14,
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ARM11_DSCR_WDTR_FULL = 1 << 29,
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ARM11_DSCR_RDTR_FULL = 1 << 30,
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ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
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ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
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ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
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ARM11_DSCR_MODE_SELECT = 1 << 14,
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ARM11_DSCR_WDTR_FULL = 1 << 29,
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ARM11_DSCR_RDTR_FULL = 1 << 30,
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};
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enum arm11_cpsr
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{
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ARM11_CPSR_T = 1 << 5,
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ARM11_CPSR_J = 1 << 24,
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ARM11_CPSR_T = 1 << 5,
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ARM11_CPSR_J = 1 << 24,
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};
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enum arm11_sc7
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{
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ARM11_SC7_NULL = 0,
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ARM11_SC7_VCR = 7,
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ARM11_SC7_PC = 8,
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ARM11_SC7_BVR0 = 64,
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ARM11_SC7_BCR0 = 80,
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ARM11_SC7_WVR0 = 96,
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ARM11_SC7_WCR0 = 112,
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ARM11_SC7_NULL = 0,
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ARM11_SC7_VCR = 7,
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ARM11_SC7_PC = 8,
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ARM11_SC7_BVR0 = 64,
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ARM11_SC7_BCR0 = 80,
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ARM11_SC7_WVR0 = 96,
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ARM11_SC7_WCR0 = 112,
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};
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typedef struct arm11_reg_state_s
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{
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u32 def_index;
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target_t * target;
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u32 def_index;
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target_t * target;
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} arm11_reg_state_t;
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/* poll current target status */
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int arm11_poll(struct target_s *target);
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/* architecture specific status reply */
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@ -230,14 +219,14 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp);
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int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm11_quit(void);
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/* helpers */
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void arm11_build_reg_cache(target_t *target);
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int arm11_set_reg(reg_t *reg, u8 *buf);
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int arm11_get_reg(reg_t *reg);
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void arm11_record_register_history(arm11_common_t * arm11);
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void arm11_dump_reg_changes(arm11_common_t * arm11);
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/* internals */
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void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
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@ -263,18 +252,17 @@ void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u3
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int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
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int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
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/** Used to make a list of read/write commands for scan chain 7
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*
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* Use with arm11_sc7_run()
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*/
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typedef struct arm11_sc7_action_s
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{
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bool write; /**< Access mode: true for write, false for read. */
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u8 address; /**< Register address mode. Use enum #arm11_sc7 */
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u32 value; /**< If write then set this to value to be written.
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In read mode this receives the read value when the
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function returns. */
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bool write; /**< Access mode: true for write, false for read. */
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u8 address; /**< Register address mode. Use enum #arm11_sc7 */
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u32 value; /**< If write then set this to value to be written.
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In read mode this receives the read value when the
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function returns. */
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} arm11_sc7_action_t;
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void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
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@ -285,6 +273,4 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
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void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
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#endif /* ARM11_H */
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@ -331,7 +331,6 @@ begin_ejtag_dma_write_b:
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
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{
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switch (size)
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@ -25,6 +25,7 @@
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#include "mips32.h"
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#include "mips_m4k.h"
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#include "mips32_dmaacc.h"
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#include "jtag.h"
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#include "log.h"
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