- remove build warnings from mips_m4k.c and arm11.c
- reformat whitespace arm11.c[ch] - add missing svn props from mips32_dmaacc.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@1032 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
parent
30e5bff4b8
commit
a5806d21d2
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@ -36,7 +36,6 @@
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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#if 0
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#define FNC_INFO LOG_DEBUG("-")
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#else
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@ -51,12 +50,10 @@
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static void arm11_on_enter_debug_state(arm11_common_t * arm11);
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bool arm11_config_memwrite_burst = true;
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bool arm11_config_memwrite_error_fatal = true;
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u32 arm11_vcr = 0;
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#define ARM11_HANDLER(x) \
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.x = arm11_##x
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@ -447,12 +444,10 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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}
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#endif
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arm11_run_instr_data_prepare(arm11);
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/* save r0 - r14 */
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/** \todo TODO: handle other mode registers */
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{size_t i;
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@ -462,7 +457,6 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
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}}
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/* save rDTR */
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/* check rDTRfull in DSCR */
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@ -545,7 +539,6 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
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}}
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}
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/** Restore processor state
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*
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* This is called in preparation for the RESTART function.
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@ -574,7 +567,6 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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arm11_run_instr_data_finish(arm11);
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/* spec says clear wDTR and rDTR; we assume they are clear as
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otherwise our programming would be sloppy */
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@ -602,13 +594,11 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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/* MSR CPSR,R0*/
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arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
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/* restore PC */
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/* MOV PC,R0 */
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arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
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/* restore R0 */
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/* MRC p14,0,r0,c0,c5,0 */
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@ -616,12 +606,10 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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arm11_run_instr_data_finish(arm11);
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/* restore DSCR */
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arm11_write_DSCR(arm11, R(DSCR));
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/* restore rDTR */
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if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
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@ -710,7 +698,6 @@ int arm11_arch_state(struct target_s *target)
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return ERROR_OK;
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}
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/* target request support */
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int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
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{
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@ -719,8 +706,6 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
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return ERROR_OK;
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}
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/* target execution control */
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int arm11_halt(struct target_s *target)
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{
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@ -775,7 +760,6 @@ int arm11_halt(struct target_s *target)
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return ERROR_OK;
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}
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int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
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{
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FNC_INFO;
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@ -845,7 +829,6 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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arm11_sc7_set_vcr(arm11, arm11_vcr);
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}
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arm11_leave_debug_state(arm11);
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arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
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@ -986,7 +969,6 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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return ERROR_OK;
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}
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/* target reset control */
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int arm11_assert_reset(struct target_s *target)
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{
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@ -1042,8 +1024,6 @@ int arm11_soft_reset_halt(struct target_s *target)
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return ERROR_OK;
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}
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/* target register access for gdb */
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int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
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{
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@ -1062,7 +1042,6 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
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(*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
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{size_t i;
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for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
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{
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@ -1075,7 +1054,6 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
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return ERROR_OK;
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}
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/* target memory access
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* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
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* count: number of items of <size>
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@ -1252,12 +1230,8 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
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}
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#endif
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arm11_run_instr_data_finish(arm11);
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return ERROR_OK;
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}
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@ -1276,7 +1250,6 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8
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return arm11_write_memory(target, address, 4, count, buffer);
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}
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int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
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{
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FNC_INFO_NOTIMPLEMENTED;
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@ -1284,7 +1257,6 @@ int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
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return ERROR_OK;
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}
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/* target break-/watchpoint control
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* rw: 0 = write, 1 = read, 2 = access
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*/
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@ -1385,7 +1357,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
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}
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cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
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LOG_DEBUG("Save CPSR: 0x%x",i,cpsr);
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LOG_DEBUG("Save CPSR: 0x%x", cpsr);
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for (i = 0; i < num_mem_params; i++)
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{
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@ -1396,7 +1368,6 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
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for (i = 0; i < num_reg_params; i++)
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{
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reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
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u32 val;
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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@ -1499,10 +1470,10 @@ restore:
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{
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LOG_DEBUG("restoring register %s with value 0x%8.8x",
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arm11->reg_list[i].name, context[i]);
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arm11_set_reg(&arm11->reg_list[i], &context[i]);
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arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
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}
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LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
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arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], &cpsr);
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arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
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// arm11->core_state = core_state;
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// arm11->core_mode = core_mode;
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@ -1614,7 +1585,6 @@ int arm11_examine(struct target_s *target)
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arm11_build_reg_cache(target);
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/* as a side-effect this reads DSCR and thus
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* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
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* as suggested by the spec.
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@ -1673,7 +1643,6 @@ int arm11_set_reg(reg_t *reg, u8 *buf)
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return ERROR_OK;
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}
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void arm11_build_reg_cache(target_t *target)
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{
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arm11_common_t *arm11 = target->arch_info;
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@ -1734,8 +1703,6 @@ void arm11_build_reg_cache(target_t *target)
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}
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}
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int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
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{
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if (argc == 0)
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@ -1771,7 +1738,6 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
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return ERROR_OK;
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}
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#define BOOL_WRAPPER(name, print_name) \
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int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
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{ \
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@ -1791,11 +1757,9 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
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#define RC_FINAL_BOOL(name, descr, var) \
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register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
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BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
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BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
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int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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if (argc == 1)
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@ -1824,7 +1788,6 @@ const u32 arm11_coproc_instruction_limits[] =
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const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
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const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
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arm11_common_t * arm11_find_target(const char * arg)
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{
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size_t jtag_target = strtoul(arg, NULL, 0);
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@ -1871,7 +1834,6 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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return ERROR_TARGET_NOT_HALTED;
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}
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u32 values[6];
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{size_t i;
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@ -1898,7 +1860,6 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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if (read)
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instr |= 0x00100000;
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arm11_run_instr_data_prepare(arm11);
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if (read)
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@ -28,13 +28,11 @@
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#include "arm_jtag.h"
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#include <stdbool.h>
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#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
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#define NEW(type, variable, items) \
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type * variable = calloc(1, sizeof(type) * items)
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/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
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#ifndef __MSVCRT__
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@ -43,7 +41,6 @@
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#define ZU "%Iu"
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#endif
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#define ARM11_REGCACHE_MODEREGS 0
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#define ARM11_REGCACHE_FREGS 0
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@ -51,7 +48,6 @@
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23 * ARM11_REGCACHE_MODEREGS + \
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9 * ARM11_REGCACHE_FREGS)
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typedef struct arm11_register_history_s
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{
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u32 value;
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@ -86,7 +82,6 @@ typedef struct arm11_common_s
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debug_version; /**< ARM debug architecture from DIDR */
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/*@}*/
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u32 last_dscr; /**< Last retrieved DSCR value;
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* Can be used to detect changes */
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@ -105,7 +100,6 @@ typedef struct arm11_common_s
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arm11_register_history_t
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reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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@ -169,17 +163,12 @@ enum arm11_sc7
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ARM11_SC7_WCR0 = 112,
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};
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typedef struct arm11_reg_state_s
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{
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u32 def_index;
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target_t * target;
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} arm11_reg_state_t;
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/* poll current target status */
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int arm11_poll(struct target_s *target);
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/* architecture specific status reply */
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@ -230,14 +219,14 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp);
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int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm11_quit(void);
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/* helpers */
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void arm11_build_reg_cache(target_t *target);
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int arm11_set_reg(reg_t *reg, u8 *buf);
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int arm11_get_reg(reg_t *reg);
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void arm11_record_register_history(arm11_common_t * arm11);
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void arm11_dump_reg_changes(arm11_common_t * arm11);
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/* internals */
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void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
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@ -263,7 +252,6 @@ void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u3
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int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
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int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
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/** Used to make a list of read/write commands for scan chain 7
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*
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* Use with arm11_sc7_run()
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@ -285,6 +273,4 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
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void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
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#endif /* ARM11_H */
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@ -331,7 +331,6 @@ begin_ejtag_dma_write_b:
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
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{
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switch (size)
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@ -25,6 +25,7 @@
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#include "mips32.h"
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#include "mips_m4k.h"
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#include "mips32_dmaacc.h"
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#include "jtag.h"
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#include "log.h"
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