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- remove build warnings from mips_m4k.c and arm11.c 

- reformat whitespace arm11.c[ch]
- add missing svn props from mips32_dmaacc.[ch]

git-svn-id: svn://svn.berlios.de/openocd/trunk@1032 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-10-08 20:16:51 +00:00
parent 30e5bff4b8
commit a5806d21d2
6 changed files with 1363 additions and 1416 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
contrib/libdcc/dcc_stdio.c
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@ -32,24 +32,24 @@
* DCRDR[23:16] is used for by host for status * DCRDR[23:16] is used for by host for status
* DCRDR[31:24] is used for by host for write buffer */ * DCRDR[31:24] is used for by host for write buffer */
#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8)) #define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
#define TARGET_REQ_TRACEMSG 0x00 #define TARGET_REQ_TRACEMSG 0x00
#define TARGET_REQ_DEBUGMSG_ASCII 0x01 #define TARGET_REQ_DEBUGMSG_ASCII 0x01
#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8)) #define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
#define TARGET_REQ_DEBUGCHAR 0x02 #define TARGET_REQ_DEBUGCHAR 0x02
#define BUSY 1 #define BUSY 1
void dbg_write(unsigned long dcc_data) void dbg_write(unsigned long dcc_data)
{ {
int len = 4; int len = 4;
while (len--) while (len--)
{ {
/* wait for data ready */ /* wait for data ready */
while (NVIC_DBG_DATA_R & BUSY); while (NVIC_DBG_DATA_R & BUSY);
/* write our data and set write flag - tell host there is data*/ /* write our data and set write flag - tell host there is data*/
NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY); NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);
dcc_data >>= 8; dcc_data >>= 8;
@ -57,15 +57,15 @@ void dbg_write(unsigned long dcc_data)
} }
#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) #elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__)
void dbg_write(unsigned long dcc_data) void dbg_write(unsigned long dcc_data)
{ {
unsigned long dcc_status; unsigned long dcc_status;
do { do {
asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status)); asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status));
} while (dcc_status & 0x2); } while (dcc_status & 0x2);
asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data)); asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data));
} }
@ -74,18 +74,18 @@ void dbg_write(unsigned long dcc_data)
#endif #endif
void dbg_trace_point(unsigned long number) void dbg_trace_point(unsigned long number)
{ {
dbg_write(TARGET_REQ_TRACEMSG | (number << 8)); dbg_write(TARGET_REQ_TRACEMSG | (number << 8));
} }
void dbg_write_u32(const unsigned long *val, long len) void dbg_write_u32(const unsigned long *val, long len)
{ {
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16)); dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));
while (len > 0) while (len > 0)
{ {
dbg_write(*val); dbg_write(*val);
val++; val++;
len--; len--;
} }
@ -94,23 +94,23 @@ void dbg_write_u32(const unsigned long *val, long len)
void dbg_write_u16(const unsigned short *val, long len) void dbg_write_u16(const unsigned short *val, long len)
{ {
unsigned long dcc_data; unsigned long dcc_data;
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16)); dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));
while (len > 0) while (len > 0)
{ {
dcc_data = val[0] dcc_data = val[0]
| ((len > 1) ? val[1] << 16: 0x0000); | ((len > 1) ? val[1] << 16: 0x0000);
dbg_write(dcc_data); dbg_write(dcc_data);
val += 2; val += 2;
len -= 2; len -= 2;
} }
} }
void dbg_write_u8(const unsigned char *val, long len) void dbg_write_u8(const unsigned char *val, long len)
{ {
unsigned long dcc_data; unsigned long dcc_data;
dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16)); dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));
@ -121,9 +121,9 @@ void dbg_write_u8(const unsigned char *val, long len)
| ((len > 1) ? val[1] << 8 : 0x00) | ((len > 1) ? val[1] << 8 : 0x00)
| ((len > 2) ? val[2] << 16 : 0x00) | ((len > 2) ? val[2] << 16 : 0x00)
| ((len > 3) ? val[3] << 24 : 0x00); | ((len > 3) ? val[3] << 24 : 0x00);
dbg_write(dcc_data); dbg_write(dcc_data);
val += 4; val += 4;
len -= 4; len -= 4;
} }
@ -133,11 +133,11 @@ void dbg_write_str(const char *msg)
{ {
long len; long len;
unsigned long dcc_data; unsigned long dcc_data;
for (len = 0; msg[len] && (len < 65536); len++); for (len = 0; msg[len] && (len < 65536); len++);
dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16)); dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));
while (len > 0) while (len > 0)
{ {
dcc_data = msg[0] dcc_data = msg[0]
@ -152,6 +152,6 @@ void dbg_write_str(const char *msg)
} }
void dbg_write_char(char msg) void dbg_write_char(char msg)
{ {
dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16)); dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));
} }

1583
src/target/arm11.c
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File diff suppressed because it is too large Load Diff

162
src/target/arm11.h
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@ -28,12 +28,10 @@
#include "arm_jtag.h" #include "arm_jtag.h"
#include <stdbool.h> #include <stdbool.h>
#define asizeof(x) (sizeof(x) / sizeof((x)[0])) #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
#define NEW(type, variable, items) \ #define NEW(type, variable, items) \
type * variable = calloc(1, sizeof(type) * items) type * variable = calloc(1, sizeof(type) * items)
/* For MinGW use 'I' prefix to print size_t (instead of 'z') */ /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
@ -43,7 +41,6 @@
#define ZU "%Iu" #define ZU "%Iu"
#endif #endif
#define ARM11_REGCACHE_MODEREGS 0 #define ARM11_REGCACHE_MODEREGS 0
#define ARM11_REGCACHE_FREGS 0 #define ARM11_REGCACHE_FREGS 0
@ -51,63 +48,60 @@
23 * ARM11_REGCACHE_MODEREGS + \ 23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS) 9 * ARM11_REGCACHE_FREGS)
typedef struct arm11_register_history_s typedef struct arm11_register_history_s
{ {
u32 value; u32 value;
u8 valid; u8 valid;
}arm11_register_history_t; }arm11_register_history_t;
enum arm11_debug_version enum arm11_debug_version
{ {
ARM11_DEBUG_V6 = 0x01, ARM11_DEBUG_V6 = 0x01,
ARM11_DEBUG_V61 = 0x02, ARM11_DEBUG_V61 = 0x02,
ARM11_DEBUG_V7 = 0x03, ARM11_DEBUG_V7 = 0x03,
ARM11_DEBUG_V7_CP14 = 0x04, ARM11_DEBUG_V7_CP14 = 0x04,
}; };
typedef struct arm11_common_s typedef struct arm11_common_s
{ {
target_t * target; target_t * target;
arm_jtag_t jtag_info; arm_jtag_t jtag_info;
/** \name Processor type detection */ /** \name Processor type detection */
/*@{*/ /*@{*/
u32 device_id; /**< IDCODE readout */ u32 device_id; /**< IDCODE readout */
u32 didr; /**< DIDR readout (debug capabilities) */ u32 didr; /**< DIDR readout (debug capabilities) */
u8 implementor; /**< DIDR Implementor readout */ u8 implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
enum arm11_debug_version
debug_version; /**< ARM debug architecture from DIDR */
/*@}*/
enum arm11_debug_version u32 last_dscr; /**< Last retrieved DSCR value;
debug_version; /**< ARM debug architecture from DIDR */ * Can be used to detect changes */
/*@}*/
bool trst_active;
bool halt_requested;
bool simulate_reset_on_next_halt;
u32 last_dscr; /**< Last retrieved DSCR value; /** \name Shadow registers to save processor state */
* Can be used to detect changes */ /*@{*/
bool trst_active; reg_t * reg_list; /**< target register list */
bool halt_requested; u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
bool simulate_reset_on_next_halt;
/** \name Shadow registers to save processor state */ /*@}*/
/*@{*/
reg_t * reg_list; /**< target register list */ arm11_register_history_t
u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
arm11_register_history_t
reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA // GA
reg_cache_t *core_cache; reg_cache_t *core_cache;
@ -121,65 +115,60 @@ typedef struct arm11_common_s
*/ */
enum arm11_instructions enum arm11_instructions
{ {
ARM11_EXTEST = 0x00, ARM11_EXTEST = 0x00,
ARM11_SCAN_N = 0x02, ARM11_SCAN_N = 0x02,
ARM11_RESTART = 0x04, ARM11_RESTART = 0x04,
ARM11_HALT = 0x08, ARM11_HALT = 0x08,
ARM11_INTEST = 0x0C, ARM11_INTEST = 0x0C,
ARM11_ITRSEL = 0x1D, ARM11_ITRSEL = 0x1D,
ARM11_IDCODE = 0x1E, ARM11_IDCODE = 0x1E,
ARM11_BYPASS = 0x1F, ARM11_BYPASS = 0x1F,
}; };
enum arm11_dscr enum arm11_dscr
{ {
ARM11_DSCR_CORE_HALTED = 1 << 0, ARM11_DSCR_CORE_HALTED = 1 << 0,
ARM11_DSCR_CORE_RESTARTED = 1 << 1, ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
ARM11_DSCR_MODE_SELECT = 1 << 14, ARM11_DSCR_MODE_SELECT = 1 << 14,
ARM11_DSCR_WDTR_FULL = 1 << 29, ARM11_DSCR_WDTR_FULL = 1 << 29,
ARM11_DSCR_RDTR_FULL = 1 << 30, ARM11_DSCR_RDTR_FULL = 1 << 30,
}; };
enum arm11_cpsr enum arm11_cpsr
{ {
ARM11_CPSR_T = 1 << 5, ARM11_CPSR_T = 1 << 5,
ARM11_CPSR_J = 1 << 24, ARM11_CPSR_J = 1 << 24,
}; };
enum arm11_sc7 enum arm11_sc7
{ {
ARM11_SC7_NULL = 0, ARM11_SC7_NULL = 0,
ARM11_SC7_VCR = 7, ARM11_SC7_VCR = 7,
ARM11_SC7_PC = 8, ARM11_SC7_PC = 8,
ARM11_SC7_BVR0 = 64, ARM11_SC7_BVR0 = 64,
ARM11_SC7_BCR0 = 80, ARM11_SC7_BCR0 = 80,
ARM11_SC7_WVR0 = 96, ARM11_SC7_WVR0 = 96,
ARM11_SC7_WCR0 = 112, ARM11_SC7_WCR0 = 112,
}; };
typedef struct arm11_reg_state_s typedef struct arm11_reg_state_s
{ {
u32 def_index; u32 def_index;
target_t * target; target_t * target;
} arm11_reg_state_t; } arm11_reg_state_t;
/* poll current target status */ /* poll current target status */
int arm11_poll(struct target_s *target); int arm11_poll(struct target_s *target);
/* architecture specific status reply */ /* architecture specific status reply */
@ -230,14 +219,14 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp);
int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_quit(void); int arm11_quit(void);
/* helpers */ /* helpers */
void arm11_build_reg_cache(target_t *target); void arm11_build_reg_cache(target_t *target);
int arm11_set_reg(reg_t *reg, u8 *buf);
int arm11_get_reg(reg_t *reg);
void arm11_record_register_history(arm11_common_t * arm11); void arm11_record_register_history(arm11_common_t * arm11);
void arm11_dump_reg_changes(arm11_common_t * arm11); void arm11_dump_reg_changes(arm11_common_t * arm11);
/* internals */ /* internals */
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field); void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
@ -263,18 +252,17 @@ void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u3
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
/** Used to make a list of read/write commands for scan chain 7 /** Used to make a list of read/write commands for scan chain 7
* *
* Use with arm11_sc7_run() * Use with arm11_sc7_run()
*/ */
typedef struct arm11_sc7_action_s typedef struct arm11_sc7_action_s
{ {
bool write; /**< Access mode: true for write, false for read. */ bool write; /**< Access mode: true for write, false for read. */
u8 address; /**< Register address mode. Use enum #arm11_sc7 */ u8 address; /**< Register address mode. Use enum #arm11_sc7 */
u32 value; /**< If write then set this to value to be written. u32 value; /**< If write then set this to value to be written.
In read mode this receives the read value when the In read mode this receives the read value when the
function returns. */ function returns. */
} arm11_sc7_action_t; } arm11_sc7_action_t;
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count); void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
@ -285,6 +273,4 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result); void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
#endif /* ARM11_H */ #endif /* ARM11_H */

881
src/target/mips32_dmaacc.c
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@ -1,441 +1,440 @@
/*************************************************************************** /***************************************************************************
* Copyright (C) 2008 by John McCarthy * * Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca * * jgmcc@magma.ca *
* * * *
* Copyright (C) 2008 by Spencer Oliver * * Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk * * spen@spen-soft.co.uk *
* * * *
* Copyright (C) 2008 by David T.L. Wong * * Copyright (C) 2008 by David T.L. Wong *
* * * *
* This program is free software; you can redistribute it and/or modify * * This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by * * it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * * the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * * (at your option) any later version. *
* * * *
* This program is distributed in the hope that it will be useful, * * This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of * * but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * * GNU General Public License for more details. *
* * * *
* You should have received a copy of the GNU General Public License * * You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the * * along with this program; if not, write to the *
* Free Software Foundation, Inc., * * Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/ ***************************************************************************/
#ifdef HAVE_CONFIG_H #ifdef HAVE_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#include <string.h> #include <string.h>
#include "log.h" #include "log.h"
#include "mips32.h" #include "mips32.h"
#include "mips32_dmaacc.h" #include "mips32_dmaacc.h"
/* /*
* The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
* to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
* (and any others that support EJTAG DMA transfers). * (and any others that support EJTAG DMA transfers).
* Note: This only supports memory read/write. Since the BCM5352 doesn't * Note: This only supports memory read/write. Since the BCM5352 doesn't
* appear to support PRACC accesses, all debug functions except halt * appear to support PRACC accesses, all debug functions except halt
* do not work. Still, this does allow erasing/writing flash as well as * do not work. Still, this does allow erasing/writing flash as well as
* displaying/modifying memory and memory mapped registers. * displaying/modifying memory and memory mapped registers.
*/ */
static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data) static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read: begin_ejtag_dma_read:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT // Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Read Data // Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, data); mips_ejtag_drscan_32(ejtag_info, data);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read; goto begin_ejtag_dma_read;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
return ERROR_OK; return ERROR_OK;
} }
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data) static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read_h: begin_ejtag_dma_read_h:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT // Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Read Data // Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read_h; goto begin_ejtag_dma_read_h;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
// Handle the bigendian/littleendian // Handle the bigendian/littleendian
if ( addr & 0x2 ) *data = (v>>16)&0xffff ; if ( addr & 0x2 ) *data = (v>>16)&0xffff ;
else *data = (v&0x0000ffff) ; else *data = (v&0x0000ffff) ;
return ERROR_OK; return ERROR_OK;
} }
static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data) static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read_b: begin_ejtag_dma_read_b:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT // Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Read Data // Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read_b; goto begin_ejtag_dma_read_b;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
// Handle the bigendian/littleendian // Handle the bigendian/littleendian
switch(addr & 0x3) { switch(addr & 0x3) {
case 0: *data = v & 0xff; break; case 0: *data = v & 0xff; break;
case 1: *data = (v>>8) & 0xff; break; case 1: *data = (v>>8) & 0xff; break;
case 2: *data = (v>>16) & 0xff; break; case 2: *data = (v>>16) & 0xff; break;
case 3: *data = (v>>24) & 0xff; break; case 3: *data = (v>>24) & 0xff; break;
} }
return ERROR_OK; return ERROR_OK;
} }
static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data) static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_write: begin_ejtag_dma_write:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data // Setup Data
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT // Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write; goto begin_ejtag_dma_write;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
return ERROR_OK; return ERROR_OK;
} }
static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data) static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
// Handle the bigendian/littleendian // Handle the bigendian/littleendian
data &= 0xffff; data &= 0xffff;
data |= data<<16; data |= data<<16;
begin_ejtag_dma_write_h: begin_ejtag_dma_write_h:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data // Setup Data
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT // Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write_h; goto begin_ejtag_dma_write_h;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
return ERROR_OK; return ERROR_OK;
} }
static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data) static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{ {
u32 v; u32 v;
u32 ctrl_reg; u32 ctrl_reg;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
// Handle the bigendian/littleendian // Handle the bigendian/littleendian
data &= 0xff; data &= 0xff;
data |= data<<8; data |= data<<8;
data |= data<<16; data |= data<<16;
begin_ejtag_dma_write_b: begin_ejtag_dma_write_b:
// Setup Address // Setup Address
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data // Setup Data
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT // Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
// Wait for DSTRT to Clear // Wait for DSTRT to Clear
do { do {
ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
} while(ctrl_reg & EJTAG_CTRL_DSTRT); } while(ctrl_reg & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR // Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC; ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
mips_ejtag_drscan_32(ejtag_info, &ctrl_reg); mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
if (ctrl_reg & EJTAG_CTRL_DERR) if (ctrl_reg & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write_b; goto begin_ejtag_dma_write_b;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
return ERROR_OK; return ERROR_OK;
} }
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) {
{ switch (size)
switch (size) {
{ case 1:
case 1: return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf); case 2:
case 2: return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf); case 4:
case 4: return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf); }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) {
{ switch (size)
switch (size) {
{ case 1:
case 1: return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf); case 2:
case 2: return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf); case 4:
case 4: return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf); }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}
int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf) {
{ int i;
int i; int retval;
int retval;
for(i=0; i<count; i++) {
for(i=0; i<count; i++) { if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) return retval;
return retval; }
}
return ERROR_OK;
return ERROR_OK; }
}

106
src/target/mips32_dmaacc.h
View File

@ -1,53 +1,53 @@
/*************************************************************************** /***************************************************************************
* Copyright (C) 2008 by John McCarthy * * Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca * * jgmcc@magma.ca *
* * * *
* Copyright (C) 2008 by Spencer Oliver * * Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk * * spen@spen-soft.co.uk *
* * * *
* Copyright (C) 2008 by David T.L. Wong * * Copyright (C) 2008 by David T.L. Wong *
* * * *
* This program is free software; you can redistribute it and/or modify * * This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by * * it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * * the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * * (at your option) any later version. *
* * * *
* This program is distributed in the hope that it will be useful, * * This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of * * but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * * GNU General Public License for more details. *
* * * *
* You should have received a copy of the GNU General Public License * * You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the * * along with this program; if not, write to the *
* Free Software Foundation, Inc., * * Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/ ***************************************************************************/
#ifndef MIPS32_DMAACC_H #ifndef MIPS32_DMAACC_H
#define MIPS32_DMAACC_H #define MIPS32_DMAACC_H
#include "mips_ejtag.h" #include "mips_ejtag.h"
#define EJTAG_CTRL_DMA_BYTE 0x00000000 #define EJTAG_CTRL_DMA_BYTE 0x00000000
#define EJTAG_CTRL_DMA_HALFWORD 0x00000080 #define EJTAG_CTRL_DMA_HALFWORD 0x00000080
#define EJTAG_CTRL_DMA_WORD 0x00000100 #define EJTAG_CTRL_DMA_WORD 0x00000100
#define EJTAG_CTRL_DMA_TRIPLEBYTE 0x00000180 #define EJTAG_CTRL_DMA_TRIPLEBYTE 0x00000180
#define RETRY_ATTEMPTS 4 #define RETRY_ATTEMPTS 4
extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf); extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf); extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf); extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf); extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf); extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf); extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf); extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf); extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
#if 0 #if 0
extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs); extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);
extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs); extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);
#endif #endif
#endif #endif

1
src/target/mips_m4k.c
View File

@ -25,6 +25,7 @@
#include "mips32.h" #include "mips32.h"
#include "mips_m4k.h" #include "mips_m4k.h"
#include "mips32_dmaacc.h"
#include "jtag.h" #include "jtag.h"
#include "log.h" #include "log.h"