interesting
/
riscv-openocd
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

- remove build warnings from mips_m4k.c and arm11.c 

- reformat whitespace arm11.c[ch]
- add missing svn props from mips32_dmaacc.[ch]

git-svn-id: svn://svn.berlios.de/openocd/trunk@1032 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-10-08 20:16:51 +00:00
parent 30e5bff4b8
commit a5806d21d2
6 changed files with 1363 additions and 1416 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
contrib/libdcc/dcc_stdio.c
View File

@ -32,12 +32,12 @@
* DCRDR[23:16] is used for by host for status * DCRDR[23:16] is used for by host for status
* DCRDR[31:24] is used for by host for write buffer */ * DCRDR[31:24] is used for by host for write buffer */
#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8)) #define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
#define TARGET_REQ_TRACEMSG 0x00 #define TARGET_REQ_TRACEMSG 0x00
#define TARGET_REQ_DEBUGMSG_ASCII 0x01 #define TARGET_REQ_DEBUGMSG_ASCII 0x01
#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8)) #define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
#define TARGET_REQ_DEBUGCHAR 0x02 #define TARGET_REQ_DEBUGCHAR 0x02
#define BUSY 1 #define BUSY 1

1581
src/target/arm11.c
View File

File diff suppressed because it is too large Load Diff

160
src/target/arm11.h
View File

@ -28,12 +28,10 @@
#include "arm_jtag.h" #include "arm_jtag.h"
#include <stdbool.h> #include <stdbool.h>
#define asizeof(x) (sizeof(x) / sizeof((x)[0])) #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
#define NEW(type, variable, items) \ #define NEW(type, variable, items) \
type * variable = calloc(1, sizeof(type) * items) type * variable = calloc(1, sizeof(type) * items)
/* For MinGW use 'I' prefix to print size_t (instead of 'z') */ /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
@ -43,7 +41,6 @@
#define ZU "%Iu" #define ZU "%Iu"
#endif #endif
#define ARM11_REGCACHE_MODEREGS 0 #define ARM11_REGCACHE_MODEREGS 0
#define ARM11_REGCACHE_FREGS 0 #define ARM11_REGCACHE_FREGS 0
@ -51,63 +48,60 @@
23 * ARM11_REGCACHE_MODEREGS + \ 23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS) 9 * ARM11_REGCACHE_FREGS)
typedef struct arm11_register_history_s typedef struct arm11_register_history_s
{ {
u32 value; u32 value;
u8 valid; u8 valid;
}arm11_register_history_t; }arm11_register_history_t;
enum arm11_debug_version enum arm11_debug_version
{ {
ARM11_DEBUG_V6 = 0x01, ARM11_DEBUG_V6 = 0x01,
ARM11_DEBUG_V61 = 0x02, ARM11_DEBUG_V61 = 0x02,
ARM11_DEBUG_V7 = 0x03, ARM11_DEBUG_V7 = 0x03,
ARM11_DEBUG_V7_CP14 = 0x04, ARM11_DEBUG_V7_CP14 = 0x04,
}; };
typedef struct arm11_common_s typedef struct arm11_common_s
{ {
target_t * target; target_t * target;
arm_jtag_t jtag_info; arm_jtag_t jtag_info;
/** \name Processor type detection */ /** \name Processor type detection */
/*@{*/ /*@{*/
u32 device_id; /**< IDCODE readout */ u32 device_id; /**< IDCODE readout */
u32 didr; /**< DIDR readout (debug capabilities) */ u32 didr; /**< DIDR readout (debug capabilities) */
u8 implementor; /**< DIDR Implementor readout */ u8 implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
enum arm11_debug_version enum arm11_debug_version
debug_version; /**< ARM debug architecture from DIDR */ debug_version; /**< ARM debug architecture from DIDR */
/*@}*/ /*@}*/
u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */
u32 last_dscr; /**< Last retrieved DSCR value; bool trst_active;
* Can be used to detect changes */ bool halt_requested;
bool simulate_reset_on_next_halt;
bool trst_active; /** \name Shadow registers to save processor state */
bool halt_requested; /*@{*/
bool simulate_reset_on_next_halt;
/** \name Shadow registers to save processor state */ reg_t * reg_list; /**< target register list */
/*@{*/ u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
reg_t * reg_list; /**< target register list */ /*@}*/
u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/ arm11_register_history_t
arm11_register_history_t
reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA // GA
reg_cache_t *core_cache; reg_cache_t *core_cache;
@ -121,65 +115,60 @@ typedef struct arm11_common_s
*/ */
enum arm11_instructions enum arm11_instructions
{ {
ARM11_EXTEST = 0x00, ARM11_EXTEST = 0x00,
ARM11_SCAN_N = 0x02, ARM11_SCAN_N = 0x02,
ARM11_RESTART = 0x04, ARM11_RESTART = 0x04,
ARM11_HALT = 0x08, ARM11_HALT = 0x08,
ARM11_INTEST = 0x0C, ARM11_INTEST = 0x0C,
ARM11_ITRSEL = 0x1D, ARM11_ITRSEL = 0x1D,
ARM11_IDCODE = 0x1E, ARM11_IDCODE = 0x1E,
ARM11_BYPASS = 0x1F, ARM11_BYPASS = 0x1F,
}; };
enum arm11_dscr enum arm11_dscr
{ {
ARM11_DSCR_CORE_HALTED = 1 << 0, ARM11_DSCR_CORE_HALTED = 1 << 0,
ARM11_DSCR_CORE_RESTARTED = 1 << 1, ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
ARM11_DSCR_MODE_SELECT = 1 << 14, ARM11_DSCR_MODE_SELECT = 1 << 14,
ARM11_DSCR_WDTR_FULL = 1 << 29, ARM11_DSCR_WDTR_FULL = 1 << 29,
ARM11_DSCR_RDTR_FULL = 1 << 30, ARM11_DSCR_RDTR_FULL = 1 << 30,
}; };
enum arm11_cpsr enum arm11_cpsr
{ {
ARM11_CPSR_T = 1 << 5, ARM11_CPSR_T = 1 << 5,
ARM11_CPSR_J = 1 << 24, ARM11_CPSR_J = 1 << 24,
}; };
enum arm11_sc7 enum arm11_sc7
{ {
ARM11_SC7_NULL = 0, ARM11_SC7_NULL = 0,
ARM11_SC7_VCR = 7, ARM11_SC7_VCR = 7,
ARM11_SC7_PC = 8, ARM11_SC7_PC = 8,
ARM11_SC7_BVR0 = 64, ARM11_SC7_BVR0 = 64,
ARM11_SC7_BCR0 = 80, ARM11_SC7_BCR0 = 80,
ARM11_SC7_WVR0 = 96, ARM11_SC7_WVR0 = 96,
ARM11_SC7_WCR0 = 112, ARM11_SC7_WCR0 = 112,
}; };
typedef struct arm11_reg_state_s typedef struct arm11_reg_state_s
{ {
u32 def_index; u32 def_index;
target_t * target; target_t * target;
} arm11_reg_state_t; } arm11_reg_state_t;
/* poll current target status */ /* poll current target status */
int arm11_poll(struct target_s *target); int arm11_poll(struct target_s *target);
/* architecture specific status reply */ /* architecture specific status reply */
@ -230,14 +219,14 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp);
int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_quit(void); int arm11_quit(void);
/* helpers */ /* helpers */
void arm11_build_reg_cache(target_t *target); void arm11_build_reg_cache(target_t *target);
int arm11_set_reg(reg_t *reg, u8 *buf);
int arm11_get_reg(reg_t *reg);
void arm11_record_register_history(arm11_common_t * arm11); void arm11_record_register_history(arm11_common_t * arm11);
void arm11_dump_reg_changes(arm11_common_t * arm11); void arm11_dump_reg_changes(arm11_common_t * arm11);
/* internals */ /* internals */
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field); void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
@ -263,18 +252,17 @@ void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u3
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
/** Used to make a list of read/write commands for scan chain 7 /** Used to make a list of read/write commands for scan chain 7
* *
* Use with arm11_sc7_run() * Use with arm11_sc7_run()
*/ */
typedef struct arm11_sc7_action_s typedef struct arm11_sc7_action_s
{ {
bool write; /**< Access mode: true for write, false for read. */ bool write; /**< Access mode: true for write, false for read. */
u8 address; /**< Register address mode. Use enum #arm11_sc7 */ u8 address; /**< Register address mode. Use enum #arm11_sc7 */
u32 value; /**< If write then set this to value to be written. u32 value; /**< If write then set this to value to be written.
In read mode this receives the read value when the In read mode this receives the read value when the
function returns. */ function returns. */
} arm11_sc7_action_t; } arm11_sc7_action_t;
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count); void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
@ -285,6 +273,4 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result); void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
#endif /* ARM11_H */ #endif /* ARM11_H */

1
src/target/mips32_dmaacc.c
View File

@ -331,7 +331,6 @@ begin_ejtag_dma_write_b:
return ERROR_OK; return ERROR_OK;
} }
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
{ {
switch (size) switch (size)

1
src/target/mips_m4k.c
View File

@ -25,6 +25,7 @@
#include "mips32.h" #include "mips32.h"
#include "mips_m4k.h" #include "mips_m4k.h"
#include "mips32_dmaacc.h"
#include "jtag.h" #include "jtag.h"
#include "log.h" #include "log.h"