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- remove build warnings from mips_m4k.c and arm11.c 

- reformat whitespace arm11.c[ch]
- add missing svn props from mips32_dmaacc.[ch]

git-svn-id: svn://svn.berlios.de/openocd/trunk@1032 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-10-08 20:16:51 +00:00
parent 30e5bff4b8
commit a5806d21d2
6 changed files with 1363 additions and 1416 deletions
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45
src/target/arm11.c
View File

@ -36,7 +36,6 @@
#define _DEBUG_INSTRUCTION_EXECUTION_ #define _DEBUG_INSTRUCTION_EXECUTION_
#endif #endif
#if 0 #if 0
#define FNC_INFO LOG_DEBUG("-") #define FNC_INFO LOG_DEBUG("-")
#else #else
@ -51,12 +50,10 @@
static void arm11_on_enter_debug_state(arm11_common_t * arm11); static void arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true; bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true; bool arm11_config_memwrite_error_fatal = true;
u32 arm11_vcr = 0; u32 arm11_vcr = 0;
#define ARM11_HANDLER(x) \ #define ARM11_HANDLER(x) \
.x = arm11_##x .x = arm11_##x
@ -447,12 +444,10 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
} }
#endif #endif
arm11_run_instr_data_prepare(arm11); arm11_run_instr_data_prepare(arm11);
/* save r0 - r14 */ /* save r0 - r14 */
/** \todo TODO: handle other mode registers */ /** \todo TODO: handle other mode registers */
{size_t i; {size_t i;
@ -462,7 +457,6 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
}} }}
/* save rDTR */ /* save rDTR */
/* check rDTRfull in DSCR */ /* check rDTRfull in DSCR */
@ -545,7 +539,6 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
}} }}
} }
/** Restore processor state /** Restore processor state
* *
* This is called in preparation for the RESTART function. * This is called in preparation for the RESTART function.
@ -574,7 +567,6 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
arm11_run_instr_data_finish(arm11); arm11_run_instr_data_finish(arm11);
/* spec says clear wDTR and rDTR; we assume they are clear as /* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */ otherwise our programming would be sloppy */
@ -602,13 +594,11 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
/* MSR CPSR,R0*/ /* MSR CPSR,R0*/
arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR)); arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
/* restore PC */ /* restore PC */
/* MOV PC,R0 */ /* MOV PC,R0 */
arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC)); arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
/* restore R0 */ /* restore R0 */
/* MRC p14,0,r0,c0,c5,0 */ /* MRC p14,0,r0,c0,c5,0 */
@ -616,12 +606,10 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
arm11_run_instr_data_finish(arm11); arm11_run_instr_data_finish(arm11);
/* restore DSCR */ /* restore DSCR */
arm11_write_DSCR(arm11, R(DSCR)); arm11_write_DSCR(arm11, R(DSCR));
/* restore rDTR */ /* restore rDTR */
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
@ -710,7 +698,6 @@ int arm11_arch_state(struct target_s *target)
return ERROR_OK; return ERROR_OK;
} }
/* target request support */ /* target request support */
int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer) int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
{ {
@ -719,8 +706,6 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
return ERROR_OK; return ERROR_OK;
} }
/* target execution control */ /* target execution control */
int arm11_halt(struct target_s *target) int arm11_halt(struct target_s *target)
{ {
@ -775,7 +760,6 @@ int arm11_halt(struct target_s *target)
return ERROR_OK; return ERROR_OK;
} }
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{ {
FNC_INFO; FNC_INFO;
@ -845,7 +829,6 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
arm11_sc7_set_vcr(arm11, arm11_vcr); arm11_sc7_set_vcr(arm11, arm11_vcr);
} }
arm11_leave_debug_state(arm11); arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
@ -986,7 +969,6 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
return ERROR_OK; return ERROR_OK;
} }
/* target reset control */ /* target reset control */
int arm11_assert_reset(struct target_s *target) int arm11_assert_reset(struct target_s *target)
{ {
@ -1042,8 +1024,6 @@ int arm11_soft_reset_halt(struct target_s *target)
return ERROR_OK; return ERROR_OK;
} }
/* target register access for gdb */ /* target register access for gdb */
int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size) int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
{ {
@ -1062,7 +1042,6 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
(*reg_list)[24] = &arm11_gdb_dummy_fps_reg; (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
{size_t i; {size_t i;
for (i = 0; i < ARM11_REGCACHE_COUNT; i++) for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{ {
@ -1075,7 +1054,6 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
return ERROR_OK; return ERROR_OK;
} }
/* target memory access /* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size> * count: number of items of <size>
@ -1252,12 +1230,8 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
} }
#endif #endif
arm11_run_instr_data_finish(arm11); arm11_run_instr_data_finish(arm11);
return ERROR_OK; return ERROR_OK;
} }
@ -1276,7 +1250,6 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8
return arm11_write_memory(target, address, 4, count, buffer); return arm11_write_memory(target, address, 4, count, buffer);
} }
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
{ {
FNC_INFO_NOTIMPLEMENTED; FNC_INFO_NOTIMPLEMENTED;
@ -1284,7 +1257,6 @@ int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
return ERROR_OK; return ERROR_OK;
} }
/* target break-/watchpoint control /* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access * rw: 0 = write, 1 = read, 2 = access
*/ */
@ -1385,7 +1357,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
} }
cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32); cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
LOG_DEBUG("Save CPSR: 0x%x",i,cpsr); LOG_DEBUG("Save CPSR: 0x%x", cpsr);
for (i = 0; i < num_mem_params; i++) for (i = 0; i < num_mem_params; i++)
{ {
@ -1396,7 +1368,6 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
for (i = 0; i < num_reg_params; i++) for (i = 0; i < num_reg_params; i++)
{ {
reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
u32 val;
if (!reg) if (!reg)
{ {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@ -1499,10 +1470,10 @@ restore:
{ {
LOG_DEBUG("restoring register %s with value 0x%8.8x", LOG_DEBUG("restoring register %s with value 0x%8.8x",
arm11->reg_list[i].name, context[i]); arm11->reg_list[i].name, context[i]);
arm11_set_reg(&arm11->reg_list[i], &context[i]); arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
} }
LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr); LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], &cpsr); arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
// arm11->core_state = core_state; // arm11->core_state = core_state;
// arm11->core_mode = core_mode; // arm11->core_mode = core_mode;
@ -1614,7 +1585,6 @@ int arm11_examine(struct target_s *target)
arm11_build_reg_cache(target); arm11_build_reg_cache(target);
/* as a side-effect this reads DSCR and thus /* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
* as suggested by the spec. * as suggested by the spec.
@ -1673,7 +1643,6 @@ int arm11_set_reg(reg_t *reg, u8 *buf)
return ERROR_OK; return ERROR_OK;
} }
void arm11_build_reg_cache(target_t *target) void arm11_build_reg_cache(target_t *target)
{ {
arm11_common_t *arm11 = target->arch_info; arm11_common_t *arm11 = target->arch_info;
@ -1734,8 +1703,6 @@ void arm11_build_reg_cache(target_t *target)
} }
} }
int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
{ {
if (argc == 0) if (argc == 0)
@ -1771,7 +1738,6 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
return ERROR_OK; return ERROR_OK;
} }
#define BOOL_WRAPPER(name, print_name) \ #define BOOL_WRAPPER(name, print_name) \
int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
{ \ { \
@ -1791,11 +1757,9 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
#define RC_FINAL_BOOL(name, descr, var) \ #define RC_FINAL_BOOL(name, descr, var) \
register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr); register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
BOOL_WRAPPER(memwrite_burst, "memory write burst mode") BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{ {
if (argc == 1) if (argc == 1)
@ -1824,7 +1788,6 @@ const u32 arm11_coproc_instruction_limits[] =
const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only."; const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only."; const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
arm11_common_t * arm11_find_target(const char * arg) arm11_common_t * arm11_find_target(const char * arg)
{ {
size_t jtag_target = strtoul(arg, NULL, 0); size_t jtag_target = strtoul(arg, NULL, 0);
@ -1871,7 +1834,6 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
u32 values[6]; u32 values[6];
{size_t i; {size_t i;
@ -1898,7 +1860,6 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (read) if (read)
instr |= 0x00100000; instr |= 0x00100000;
arm11_run_instr_data_prepare(arm11); arm11_run_instr_data_prepare(arm11);
if (read) if (read)

18
src/target/arm11.h
View File

@ -28,13 +28,11 @@
#include "arm_jtag.h" #include "arm_jtag.h"
#include <stdbool.h> #include <stdbool.h>
#define asizeof(x) (sizeof(x) / sizeof((x)[0])) #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
#define NEW(type, variable, items) \ #define NEW(type, variable, items) \
type * variable = calloc(1, sizeof(type) * items) type * variable = calloc(1, sizeof(type) * items)
/* For MinGW use 'I' prefix to print size_t (instead of 'z') */ /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
#ifndef __MSVCRT__ #ifndef __MSVCRT__
@ -43,7 +41,6 @@
#define ZU "%Iu" #define ZU "%Iu"
#endif #endif
#define ARM11_REGCACHE_MODEREGS 0 #define ARM11_REGCACHE_MODEREGS 0
#define ARM11_REGCACHE_FREGS 0 #define ARM11_REGCACHE_FREGS 0
@ -51,7 +48,6 @@
23 * ARM11_REGCACHE_MODEREGS + \ 23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS) 9 * ARM11_REGCACHE_FREGS)
typedef struct arm11_register_history_s typedef struct arm11_register_history_s
{ {
u32 value; u32 value;
@ -86,7 +82,6 @@ typedef struct arm11_common_s
debug_version; /**< ARM debug architecture from DIDR */ debug_version; /**< ARM debug architecture from DIDR */
/*@}*/ /*@}*/
u32 last_dscr; /**< Last retrieved DSCR value; u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */ * Can be used to detect changes */
@ -105,7 +100,6 @@ typedef struct arm11_common_s
arm11_register_history_t arm11_register_history_t
reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
@ -169,17 +163,12 @@ enum arm11_sc7
ARM11_SC7_WCR0 = 112, ARM11_SC7_WCR0 = 112,
}; };
typedef struct arm11_reg_state_s typedef struct arm11_reg_state_s
{ {
u32 def_index; u32 def_index;
target_t * target; target_t * target;
} arm11_reg_state_t; } arm11_reg_state_t;
/* poll current target status */ /* poll current target status */
int arm11_poll(struct target_s *target); int arm11_poll(struct target_s *target);
/* architecture specific status reply */ /* architecture specific status reply */
@ -230,14 +219,14 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp);
int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_quit(void); int arm11_quit(void);
/* helpers */ /* helpers */
void arm11_build_reg_cache(target_t *target); void arm11_build_reg_cache(target_t *target);
int arm11_set_reg(reg_t *reg, u8 *buf);
int arm11_get_reg(reg_t *reg);
void arm11_record_register_history(arm11_common_t * arm11); void arm11_record_register_history(arm11_common_t * arm11);
void arm11_dump_reg_changes(arm11_common_t * arm11); void arm11_dump_reg_changes(arm11_common_t * arm11);
/* internals */ /* internals */
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field); void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
@ -263,7 +252,6 @@ void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u3
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state); int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
/** Used to make a list of read/write commands for scan chain 7 /** Used to make a list of read/write commands for scan chain 7
* *
* Use with arm11_sc7_run() * Use with arm11_sc7_run()
@ -285,6 +273,4 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result); void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
#endif /* ARM11_H */ #endif /* ARM11_H */

1
src/target/mips32_dmaacc.c
View File

@ -331,7 +331,6 @@ begin_ejtag_dma_write_b:
return ERROR_OK; return ERROR_OK;
} }
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
{ {
switch (size) switch (size)

1
src/target/mips_m4k.c
View File

@ -25,6 +25,7 @@
#include "mips32.h" #include "mips32.h"
#include "mips_m4k.h" #include "mips_m4k.h"
#include "mips32_dmaacc.h"
#include "jtag.h" #include "jtag.h"
#include "log.h" #include "log.h"