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Merge pull request #1161 from en-sc/en-sc/deassert-reset 

target/riscv: avoid updating `target` if `ackhavereset` fails
This commit is contained in:
Evgeniy Naydanov 2024-11-14 13:23:42 +03:00 committed by GitHub
parent f7ea8245e6 784687d781
commit a2f5da3289
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GPG Key ID: B5690EEEBB952194
1 changed files with 10 additions and 7 deletions
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17
src/target/riscv/riscv-013.c
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@ -2902,6 +2902,15 @@ static int deassert_reset(struct target *target)
riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE, riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE,
orig_base_delay); orig_base_delay);
/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
control = 0;
control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
control = set_field(control, DM_DMCONTROL_ACKHAVERESET, 1);
control = set_dmcontrol_hartsel(control, info->index);
result = dm_write(target, DM_DMCONTROL, control);
if (result != ERROR_OK)
return result;
if (target->reset_halt) { if (target->reset_halt) {
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
@ -2910,13 +2919,7 @@ static int deassert_reset(struct target *target)
target->debug_reason = DBG_REASON_NOTHALTED; target->debug_reason = DBG_REASON_NOTHALTED;
} }
info->dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value(target); info->dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value(target);
return ERROR_OK;
/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
control = 0;
control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
control = set_field(control, DM_DMCONTROL_ACKHAVERESET, 1);
control = set_dmcontrol_hartsel(control, info->index);
return dm_write(target, DM_DMCONTROL, control);
} }
static int execute_fence(struct target *target) static int execute_fence(struct target *target)