fix syntax of mww phys.
This commit is contained in:
Øyvind Harboe
parent
d785f552ee
commit
a07422c26c
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@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start {
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jtag_rclk 5
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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arm926ejs mww phys 0xfffffd08 0xa5000501
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mww phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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@ -177,10 +177,10 @@ proc init_2440 { } {
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# usb clock are off 12mHz xtal
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#-----------------------------------------------
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arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
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arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
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arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
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arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
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mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
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mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
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mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
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mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
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#-----------------------------------------------
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# Configure Memory controller
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@ -188,45 +188,45 @@ proc init_2440 { } {
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# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
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#-----------------------------------------------
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arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
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arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ?
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arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
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arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
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arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
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arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
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arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
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arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
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mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
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mww phys 0x48000010 0x00001112 # BANKCON4 - ?
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mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
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mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
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mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
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mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
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mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
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mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
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#-----------------------------------------------
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# Now port configuration for enables for memory
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# and other stuff.
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#-----------------------------------------------
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arm920t mww phys 0x56000000 0x007FFFFF # GPACON
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mww phys 0x56000000 0x007FFFFF # GPACON
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arm920t mww phys 0x56000010 0x00295559 # GPBCON
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arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
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arm920t mww phys 0x56000014 0x000007C2 # GPBDAT
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mww phys 0x56000010 0x00295559 # GPBCON
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mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
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mww phys 0x56000014 0x000007C2 # GPBDAT
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arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON
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arm920t mww phys 0x56000028 0x0000FFFF # GPCUP
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arm920t mww phys 0x56000024 0x00000020 # GPCDAT
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mww phys 0x56000020 0xAAAAA6AA # GPCCON
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mww phys 0x56000028 0x0000FFFF # GPCUP
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mww phys 0x56000024 0x00000020 # GPCDAT
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arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON
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arm920t mww phys 0x56000038 0x0000FFFF # GPDUP
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mww phys 0x56000030 0xAAAAAAAA # GPDCON
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mww phys 0x56000038 0x0000FFFF # GPDUP
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arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON
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arm920t mww phys 0x56000048 0x0000FFFF # GPEUP
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mww phys 0x56000040 0xAAAAAAAA # GPECON
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mww phys 0x56000048 0x0000FFFF # GPEUP
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arm920t mww phys 0x56000050 0x00001555 # GPFCON
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arm920t mww phys 0x56000058 0x0000007F # GPFUP
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arm920t mww phys 0x56000054 0x00000000 # GPFDAT
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mww phys 0x56000050 0x00001555 # GPFCON
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mww phys 0x56000058 0x0000007F # GPFUP
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mww phys 0x56000054 0x00000000 # GPFDAT
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arm920t mww phys 0x56000060 0x00150114 # GPGCON
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arm920t mww phys 0x56000068 0x0000007F # GPGUP
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mww phys 0x56000060 0x00150114 # GPGCON
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mww phys 0x56000068 0x0000007F # GPGUP
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arm920t mww phys 0x56000070 0x0015AAAA # GPHCON
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arm920t mww phys 0x56000078 0x000003FF # GPGUP
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mww phys 0x56000070 0x0015AAAA # GPHCON
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mww phys 0x56000078 0x000003FF # GPGUP
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}
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@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
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# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
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# be enabled... use physical address.
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arm926ejs mww phys 0xfffffd08 0xa5000501
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mww phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start {
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jtag_rclk 3
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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arm926ejs mww phys 0xfffffd08 0xa5000501
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mww phys 0xfffffd08 0xa5000501
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}
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@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
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#
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# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
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arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
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mww phys [expr $timer2_phys + 0x28] 0x00004000
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#
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# Part II -- in case watchdog hasn't been set up
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#
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# TCR: disable, force internal clock source
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arm926ejs mww phys [expr $timer2_phys + 0x20] 0
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mww phys [expr $timer2_phys + 0x20] 0
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# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
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arm926ejs mww phys [expr $timer2_phys + 0x24] 0
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arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
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mww phys [expr $timer2_phys + 0x24] 0
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mww phys [expr $timer2_phys + 0x24] 0x110b
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# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
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# so watchdog triggers ASAP
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arm926ejs mww phys [expr $timer2_phys + 0x10] 0
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arm926ejs mww phys [expr $timer2_phys + 0x14] 0
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arm926ejs mww phys [expr $timer2_phys + 0x18] 0
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arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
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mww phys [expr $timer2_phys + 0x10] 0
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mww phys [expr $timer2_phys + 0x14] 0
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mww phys [expr $timer2_phys + 0x18] 0
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mww phys [expr $timer2_phys + 0x1c] 0
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# WDTCR: put into pre-active state, then active
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arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
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arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
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mww phys [expr $timer2_phys + 0x28] 0xa5c64000
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mww phys [expr $timer2_phys + 0x28] 0xda7e4000
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#
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# Part III -- it's ready to rumble
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#
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# WDTCR: write invalid WDKEY to trigger reset
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arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
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mww phys [expr $timer2_phys + 0x28] 0x00004000
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}
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