riscv: Add a option to specify the JTAG TAP tunnel IR (#690)
* riscv: Add a option to specify the JTAG TAP IR used to access the bscan tunnel. Change-Id: Ice8798823313e2177e75473e62b06e7da74bbba2 Signed-off-by: Charles Papon <charles.papon.90@gmail.com> * risc-v: Add litex doc about the set_bscan_tunnel_ir command Change-Id: I1237213f32886d20fc7d60d5ca1e2124953eaeda Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * risc-v: remove tunnel ir length assert when ir is set by the user Change-Id: I2b33fc6205f37461ff1bd15601b460a2467ea32b Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * Open riscv: Add a option to specify the JTAG TAP tunnel IR Typo Co-authored-by: Tim Newsome <tim@sifive.com> * riscv: Add a option to specify the JTAG TAP tunnel IR typo Co-authored-by: Tim Newsome <tim@sifive.com> Co-authored-by: Tim Newsome <tim@sifive.com>
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@ -10624,6 +10624,11 @@ tunneled DR scan consists of:
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@end deffn
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@deffn {Command} {riscv set_bscan_tunnel_ir} value
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Allows the use_bscan_tunnel feature to target non Xilinx device by
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specifying the JTAG TAP IR used to access the bscan tunnel.
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@end deffn
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@deffn {Command} {riscv set_maskisr} [@option{off}|@option{steponly}]
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Selects whether interrupts will be disabled when single stepping. The default configuration is @option{off}.
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This feature is only useful on hardware that always steps into interrupts and doesn't support dcsr.stepie=0.
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@ -129,6 +129,7 @@ struct scan_field select_idcode = {
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bscan_tunnel_type_t bscan_tunnel_type;
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int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
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static int bscan_tunnel_ir_id; /* IR ID of the JTAG TAP to access the tunnel. Valid when not 0 */
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static const uint8_t bscan_zero[4] = {0};
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static const uint8_t bscan_one[4] = {1};
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@ -450,8 +451,12 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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select_idcode.num_bits = target->tap->ir_length;
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if (bscan_tunnel_ir_width != 0) {
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uint32_t ir_user4_raw = bscan_tunnel_ir_id;
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/* Provide a default value which target some Xilinx FPGA USER4 IR */
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if (ir_user4_raw == 0) {
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assert(target->tap->ir_length >= 6);
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uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
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ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
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}
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ir_user4[0] = (uint8_t)ir_user4_raw;
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ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
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ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
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@ -2913,6 +2918,24 @@ COMMAND_HANDLER(riscv_use_bscan_tunnel)
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return ERROR_OK;
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}
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COMMAND_HANDLER(riscv_set_bscan_tunnel_ir)
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{
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int ir_id = 0;
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if (CMD_ARGC > 1) {
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LOG_ERROR("Command takes at most one arguments");
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return ERROR_COMMAND_SYNTAX_ERROR;
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} else if (CMD_ARGC == 1) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], ir_id);
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}
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LOG_INFO("Bscan tunnel IR 0x%x selected", ir_id);
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bscan_tunnel_ir_id = ir_id;
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return ERROR_OK;
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}
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COMMAND_HANDLER(riscv_set_maskisr)
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{
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struct target *target = get_current_target(CMD_CTX);
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@ -3347,6 +3370,15 @@ static const struct command_registration riscv_exec_command_handlers[] = {
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"(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
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"1: DATA_REGISTER}"
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},
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{
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.name = "set_bscan_tunnel_ir",
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.handler = riscv_set_bscan_tunnel_ir,
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.mode = COMMAND_ANY,
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.usage = "value",
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.help = "Specify the JTAG TAP IR used to access the bscan tunnel. "
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"By default it is 0x23 << (ir_length - 6), which map some "
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"Xilinx FPGA (IR USER4)"
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},
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{
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.name = "set_maskisr",
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.handler = riscv_set_maskisr,
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