Halt should work now.

src/target/Makefile.am

@@ -136,7 +136,7 @@ INTEL_IA32_SRC = \
 	x86_32_common.c
 
 RISCV_SRC = \
-	riscv.c
+	riscv/riscv.c
 
 noinst_HEADERS = \
 	algorithm.h \

src/target/riscv/opcodes.h

@@ -0,0 +1,155 @@
+#include "encoding.h"
+
+#define S0      8
+#define S1      9
+
+static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
+  return (value >> lo) & ((1 << (hi+1-lo)) - 1);
+}
+
+static uint32_t bit(uint32_t value, unsigned int b) {
+  return (value >> b) & 1;
+}
+
+static uint32_t jal(unsigned int rd, uint32_t imm) {
+  return (bit(imm, 20) << 31) |
+    (bits(imm, 10, 1) << 21) |
+    (bit(imm, 11) << 20) |
+    (bits(imm, 19, 12) << 12) |
+    (rd << 7) |
+    MATCH_JAL;
+}
+
+static uint32_t csrsi(unsigned int csr, uint16_t imm) {
+  return (csr << 20) |
+    (bits(imm, 4, 0) << 15) |
+    MATCH_CSRRSI;
+}
+
+/*
+static uint32_t csrci(unsigned int csr, uint16_t imm) {
+  return (csr << 20) |
+    (bits(imm, 4, 0) << 15) |
+    MATCH_CSRRCI;
+}
+
+static uint32_t csrr(unsigned int rd, unsigned int csr) {
+  return (csr << 20) | (rd << 7) | MATCH_CSRRS;
+}
+
+static uint32_t csrw(unsigned int source, unsigned int csr) {
+  return (csr << 20) | (source << 15) | MATCH_CSRRW;
+}
+
+static uint32_t fence_i(void)
+{
+  return MATCH_FENCE_I;
+}
+
+static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (src << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_SB;
+}
+
+static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (src << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_SH;
+}
+
+static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (src << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_SW;
+}
+
+static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (bits(src, 4, 0) << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_SD;
+}
+
+static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 0) << 20) |
+    (base << 15) |
+    (bits(rd, 4, 0) << 7) |
+    MATCH_LD;
+}
+
+static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 0) << 20) |
+    (base << 15) |
+    (bits(rd, 4, 0) << 7) |
+    MATCH_LW;
+}
+
+static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 0) << 20) |
+    (base << 15) |
+    (bits(rd, 4, 0) << 7) |
+    MATCH_LH;
+}
+
+static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 0) << 20) |
+    (base << 15) |
+    (bits(rd, 4, 0) << 7) |
+    MATCH_LB;
+}
+
+static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (bits(src, 4, 0) << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_FSD;
+}
+
+static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (bits(src, 4, 0) << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_FLD;
+}
+
+static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
+{
+  return (bits(imm, 11, 0) << 20) |
+    (src << 15) |
+    (dest << 7) |
+    MATCH_ADDI;
+}
+
+static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
+{
+  return (bits(imm, 11, 0) << 20) |
+    (src << 15) |
+    (dest << 7) |
+    MATCH_ORI;
+}
+
+static uint32_t nop(void)
+{
+  return addi(0, 0, 0);
+}
+*/

src/target/riscv/riscv.c

@@ -8,10 +8,16 @@
 #include "target_type.h"
 #include "log.h"
 #include "jtag/jtag.h"
+#include "opcodes.h"
 
 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
 
+#define DEBUG_ROM_START         0x800
+#define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
+#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
+#define DEBUG_RAM_START         0x400
+
 /*** JTAG registers. ***/
 
 #define DTMINFO			0x10
@@ -108,6 +114,11 @@ static uint64_t dbus_read(struct target *target, uint16_t address, uint16_t next
 	return dbus_scan(target, next_address, 0, true, false);
 }
 
+static uint64_t dbus_write(struct target *target, uint16_t address, uint64_t value)
+{
+	return dbus_scan(target, address, value, false, true);
+}
+
 static uint32_t dtminfo_read(struct target *target)
 {
 	struct scan_field field;
@@ -138,6 +149,30 @@ static uint32_t dtminfo_read(struct target *target)
 	return buf_get_u32(field.in_value, 0, 32);
 }
 
+static void dram_write32(struct target *target, unsigned int index, uint32_t value,
+		bool set_interrupt)
+{
+	// TODO: check cache to see this even needs doing.
+	uint16_t address;
+	if (index < 0x10)
+		address = index;
+	else
+		address = 0x40 + index - 0x10;
+	uint64_t dbus_value = DMCONTROL_HALTNOT | value;
+	if (set_interrupt)
+		dbus_value |= DMCONTROL_INTERRUPT;
+	dbus_write(target, address, dbus_value);
+}
+
+/* Write instruction that jumps from the specified word in Debug RAM to resume
+ * in Debug ROM. */
+static void dram_write_jump(struct target *target, unsigned int index, bool set_interrupt)
+{
+	dram_write32(target, index,
+			jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
+			set_interrupt);
+}
+
 /*** OpenOCD target functions. ***/
 
 static int riscv_init_target(struct command_context *cmd_ctx,
@@ -218,6 +253,14 @@ static int riscv_poll(struct target *target)
 	return ERROR_OK;
 }
 
+static int riscv_halt(struct target *target)
+{
+	dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
+	dram_write_jump(target, 1, true);
+
+	return ERROR_OK;
+}
+
 struct target_type riscv_target = {
 	.name = "riscv",
 
@@ -228,6 +271,8 @@ struct target_type riscv_target = {
 	/* poll current target status */
 	.poll = riscv_poll,
 
+	.halt = riscv_halt,
+
 	/* TODO: */
 	/* .virt2phys = riscv_virt2phys, */
 };