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target/stm32f7x: Clear stuck HSE clock with CSS 

Change-Id: Ica0025ea465910dd664ab546b66f4f25b271f1f5
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4570
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Christopher Head 2018-04-30 10:28:21 -07:00 committed by Andreas Fritiofson
parent 4a9a07b1c5
commit 98a07154bc
1 changed files with 39 additions and 0 deletions
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39
tcl/target/stm32f7x.cfg
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@ -84,6 +84,45 @@ $_TARGETNAME configure -event trace-config {
} }
$_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-init {
# If the HSE was previously enabled and the external clock source
# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
# properly switched back to HSI. This situation persists even over a system
# reset, including a pin reset via SRST. However, activating the clock
# security system will detect the problem and clear HSERDY to 0, which in
# turn allows the PLL to switch back to HSI properly. Since we just came
# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
# have happened; in that case, activate the clock security system to clear
# HSERDY.
if {[mrw 0x40023800] & 0x00020000} {
mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
sleep 10 ;# Wait for CSS to fire, if it wants to
mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC
sleep 1 ;# Wait for CSSF to clear
}
# If the clock security system fired, it will pend an NMI. A pending NMI
# will cause a bad time for any subsequent executing code, such as a
# programming algorithm.
if {[mrw 0xE000ED04] & 0x80000000} {
# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
# cleared by any normal means (such as ICSR or NVIC). It can only be
# cleared by entering the NMI handler or by resetting the processor.
echo "[target current]: Clock security system generated NMI. Clearing."
# Keep the old DEMCR value.
set old [mrw 0xE000EDFC]
# Enable vector catch on reset.
mww 0xE000EDFC 0x01000001
# Issue local reset via AIRCR.
mww 0xE000ED0C 0x05FA0001
# Restore old DEMCR value.
mww 0xE000EDFC $old
}
# Configure PLL to boost clock to HSI x 10 (160 MHz) # Configure PLL to boost clock to HSI x 10 (160 MHz)
mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency) mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)