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nor/at91sam3: replace helper membuf 

Helper ./src/helper/membuf.c is only used in at91sam3.c

1) Replace membuf with LOG_*

2) The original code in sam3_GetDetails() invalidates
   all the buffered output of sam3_GetInfo(). The new
   code skips sam3_GetInfo() if its output should not
   be printed.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Antonio Borneo 2010-06-14 12:22:10 +08:00 committed by Øyvind Harboe
parent 814c2a8f9a
commit 984bf15821
1 changed files with 39 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

126
src/flash/nor/at91sam3.c
View File

@ -59,7 +59,6 @@
#include "imp.h" #include "imp.h"
#include "at91sam3.h" #include "at91sam3.h"
#include <helper/membuf.h>
#include <helper/time_support.h> #include <helper/time_support.h>
#define REG_NAME_WIDTH (12) #define REG_NAME_WIDTH (12)
@ -211,8 +210,6 @@ struct sam3_chip {
struct sam3_chip_details details; struct sam3_chip_details details;
struct target *target; struct target *target;
struct sam3_cfg cfg; struct sam3_cfg cfg;
struct membuf *mbuf;
}; };
@ -1000,20 +997,6 @@ FLASHD_Lock(struct sam3_bank_private *pPrivate,
/****** END SAM3 CODE ********/ /****** END SAM3 CODE ********/
/* begin helpful debug code */ /* begin helpful debug code */
static void
sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
{
va_list ap;
va_start(ap,fmt);
if (pChip->mbuf == NULL) {
return;
}
membuf_vsprintf(pChip->mbuf, fmt, ap);
va_end(ap);
}
// print the fieldname, the field value, in dec & hex, and return field value // print the fieldname, the field value, in dec & hex, and return field value
static uint32_t static uint32_t
sam3_reg_fieldname(struct sam3_chip *pChip, sam3_reg_fieldname(struct sam3_chip *pChip,
@ -1038,7 +1021,7 @@ sam3_reg_fieldname(struct sam3_chip *pChip,
} }
// show the basics // show the basics
sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ", LOG_USER_N("\t%*s: %*d [0x%0*x] ",
REG_NAME_WIDTH, regname, REG_NAME_WIDTH, regname,
dwidth, v, dwidth, v,
hwidth, v); hwidth, v);
@ -1173,16 +1156,16 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
uint32_t rcen; uint32_t rcen;
v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1); v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
sam3_sprintf(pChip, "(main xtal enabled: %s)\n", LOG_USER_N("(main xtal enabled: %s)\n",
_yes_or_no(v)); _yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1); v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
sam3_sprintf(pChip, "(main osc bypass: %s)\n", LOG_USER_N("(main osc bypass: %s)\n",
_yes_or_no(v)); _yes_or_no(v));
rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1); rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n", LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
_yes_or_no(rcen)); _yes_or_no(rcen));
v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3); v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n", LOG_USER_N("(onchip RC-OSC freq: %s)\n",
_rc_freq[v]); _rc_freq[v]);
pChip->cfg.rc_freq = 0; pChip->cfg.rc_freq = 0;
@ -1203,14 +1186,14 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
} }
v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8); v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n", LOG_USER_N("(startup clks, time= %f uSecs)\n",
((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq))); ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1); v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
sam3_sprintf(pChip, "(mainosc source: %s)\n", LOG_USER_N("(mainosc source: %s)\n",
v ? "external xtal" : "internal RC"); v ? "external xtal" : "internal RC");
v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1); v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
sam3_sprintf(pChip, "(clock failure enabled: %s)\n", LOG_USER_N("(clock failure enabled: %s)\n",
_yes_or_no(v)); _yes_or_no(v));
} }
@ -1224,19 +1207,19 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
const char *cp; const char *cp;
sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5); sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
sam3_sprintf(pChip,"\n"); LOG_USER_N("\n");
v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3); v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
sam3_sprintf(pChip, "%s\n", eproc_names[v]); LOG_USER_N("%s\n", eproc_names[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4); v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
sam3_sprintf(pChip, "%s\n", nvpsize[v]); LOG_USER_N("%s\n", nvpsize[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4); v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
sam3_sprintf(pChip, "%s\n", nvpsize2[v]); LOG_USER_N("%s\n", nvpsize2[v]);
v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4); v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
sam3_sprintf(pChip, "%s\n", sramsize[ v ]); LOG_USER_N("%s\n", sramsize[ v ]);
v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8); v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown; cp = _unknown;
@ -1247,13 +1230,13 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
} }
} }
sam3_sprintf(pChip, "%s\n", cp); LOG_USER_N("%s\n", cp);
v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3); v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
sam3_sprintf(pChip, "%s\n", nvptype[ v ]); LOG_USER_N("%s\n", nvptype[ v ]);
v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1); v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v)); LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
} }
static void static void
@ -1263,14 +1246,14 @@ sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1); v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v)); LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16); v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
v = (v * pChip->cfg.slow_freq) / 16; v = (v * pChip->cfg.slow_freq) / 16;
pChip->cfg.mainosc_freq = v; pChip->cfg.mainosc_freq = v;
sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n", LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
_tomhz(v), _tomhz(v),
pChip->cfg.slow_freq / 1000, pChip->cfg.slow_freq / 1000,
pChip->cfg.slow_freq % 1000); pChip->cfg.slow_freq % 1000);
@ -1283,17 +1266,17 @@ sam3_explain_ckgr_plla(struct sam3_chip *pChip)
uint32_t mula,diva; uint32_t mula,diva;
diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8); diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
sam3_sprintf(pChip,"\n"); LOG_USER_N("\n");
mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11); mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
sam3_sprintf(pChip,"\n"); LOG_USER_N("\n");
pChip->cfg.plla_freq = 0; pChip->cfg.plla_freq = 0;
if (mula == 0) { if (mula == 0) {
sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n"); LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
} else if (diva == 0) { } else if (diva == 0) {
sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n"); LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
} else if (diva == 1) { } else if (diva == 1) {
pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1)); pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n", LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
_tomhz(pChip->cfg.plla_freq)); _tomhz(pChip->cfg.plla_freq));
} }
} }
@ -1334,7 +1317,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
break; break;
} }
sam3_sprintf(pChip, "%s (%3.03f Mhz)\n", LOG_USER_N("%s (%3.03f Mhz)\n",
cp, cp,
_tomhz(fin)); _tomhz(fin));
pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3); pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
@ -1374,14 +1357,14 @@ sam3_explain_mckr(struct sam3_chip *pChip)
assert(0); assert(0);
break; break;
} }
sam3_sprintf(pChip, "(%s)\n", cp); LOG_USER_N("(%s)\n", cp);
fin = fin / pdiv; fin = fin / pdiv;
// sam3 has a *SINGLE* clock - // sam3 has a *SINGLE* clock -
// other at91 series parts have divisors for these. // other at91 series parts have divisors for these.
pChip->cfg.cpu_freq = fin; pChip->cfg.cpu_freq = fin;
pChip->cfg.mclk_freq = fin; pChip->cfg.mclk_freq = fin;
pChip->cfg.fclk_freq = fin; pChip->cfg.fclk_freq = fin;
sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n", LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
_tomhz(fin)); _tomhz(fin));
} }
@ -1538,15 +1521,12 @@ sam3_GetInfo(struct sam3_chip *pChip)
const struct sam3_reg_list *pReg; const struct sam3_reg_list *pReg;
uint32_t regval; uint32_t regval;
membuf_reset(pChip->mbuf);
pReg = &(sam3_all_regs[0]); pReg = &(sam3_all_regs[0]);
while (pReg->name) { while (pReg->name) {
// display all regs // display all regs
LOG_DEBUG("Start: %s", pReg->name); LOG_DEBUG("Start: %s", pReg->name);
regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg); regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n", LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
REG_NAME_WIDTH, REG_NAME_WIDTH,
pReg->name, pReg->name,
pReg->address, pReg->address,
@ -1557,14 +1537,14 @@ sam3_GetInfo(struct sam3_chip *pChip)
LOG_DEBUG("End: %s", pReg->name); LOG_DEBUG("End: %s", pReg->name);
pReg++; pReg++;
} }
sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq)); LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq)); LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq)); LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq)); LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq)); LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n", LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
pChip->cfg.unique_id[0], pChip->cfg.unique_id[0],
pChip->cfg.unique_id[1], pChip->cfg.unique_id[1],
pChip->cfg.unique_id[2], pChip->cfg.unique_id[2],
@ -1664,11 +1644,6 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
// assumption is this runs at 32khz // assumption is this runs at 32khz
pChip->cfg.slow_freq = 32768; pChip->cfg.slow_freq = 32768;
pChip->probed = 0; pChip->probed = 0;
pChip->mbuf = membuf_new();
if (!(pChip->mbuf)) {
LOG_ERROR("no memory");
return ERROR_FAIL;
}
} }
switch (bank->base) { switch (bank->base) {
@ -1702,11 +1677,8 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
{ {
const struct sam3_chip_details *pDetails; const struct sam3_chip_details *pDetails;
struct sam3_chip *pChip; struct sam3_chip *pChip;
void *vp;
struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS]; struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
unsigned x; unsigned x;
const char *cp;
LOG_DEBUG("Begin"); LOG_DEBUG("Begin");
pDetails = all_sam3_details; pDetails = all_sam3_details;
@ -1721,16 +1693,9 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)", LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR)); (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
// Help the victim, print details about the chip // Help the victim, print details about the chip
membuf_reset(pPrivate->pChip->mbuf); LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
membuf_sprintf(pPrivate->pChip->mbuf,
"SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
pPrivate->pChip->cfg.CHIPID_CIDR); pPrivate->pChip->cfg.CHIPID_CIDR);
sam3_explain_chipid_cidr(pPrivate->pChip); sam3_explain_chipid_cidr(pPrivate->pChip);
cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
while (cp) {
LOG_INFO("%s", cp);
cp = membuf_strtok(NULL, "\n", &vp);
}
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1798,18 +1763,14 @@ _sam3_probe(struct flash_bank *bank, int noise)
LOG_DEBUG("Here"); LOG_DEBUG("Here");
r = sam3_GetInfo(pPrivate->pChip); if (pPrivate->pChip->probed) {
r = sam3_GetInfo(pPrivate->pChip);
} else {
r = sam3_GetDetails(pPrivate);
}
if (r != ERROR_OK) { if (r != ERROR_OK) {
return r; return r;
} }
if (!(pPrivate->pChip->probed)) {
pPrivate->pChip->probed = 1;
LOG_DEBUG("Here");
r = sam3_GetDetails(pPrivate);
if (r != ERROR_OK) {
return r;
}
}
// update the flash bank size // update the flash bank size
for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) { for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
@ -2256,8 +2217,6 @@ sam3_write(struct flash_bank *bank,
COMMAND_HANDLER(sam3_handle_info_command) COMMAND_HANDLER(sam3_handle_info_command)
{ {
struct sam3_chip *pChip; struct sam3_chip *pChip;
void *vp;
const char *cp;
unsigned x; unsigned x;
int r; int r;
@ -2319,13 +2278,6 @@ COMMAND_HANDLER(sam3_handle_info_command)
return r; return r;
} }
// print results
cp = membuf_strtok(pChip->mbuf, "\n", &vp);
while (cp) {
command_print(CMD_CTX,"%s", cp);
cp = membuf_strtok(NULL, "\n", &vp);
}
return ERROR_OK; return ERROR_OK;
} }