nor/at91sam3: replace helper membuf
Helper ./src/helper/membuf.c is only used in at91sam3.c 1) Replace membuf with LOG_* 2) The original code in sam3_GetDetails() invalidates all the buffered output of sam3_GetInfo(). The new code skips sam3_GetInfo() if its output should not be printed. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Antonio Borneo
Øyvind Harboe
parent
814c2a8f9a
commit
984bf15821
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@ -59,7 +59,6 @@
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#include "imp.h"
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#include "at91sam3.h"
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#include <helper/membuf.h>
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#include <helper/time_support.h>
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#define REG_NAME_WIDTH (12)
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@ -211,8 +210,6 @@ struct sam3_chip {
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struct sam3_chip_details details;
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struct target *target;
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struct sam3_cfg cfg;
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struct membuf *mbuf;
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};
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@ -1000,20 +997,6 @@ FLASHD_Lock(struct sam3_bank_private *pPrivate,
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/****** END SAM3 CODE ********/
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/* begin helpful debug code */
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static void
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sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
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{
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va_list ap;
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va_start(ap,fmt);
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if (pChip->mbuf == NULL) {
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return;
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}
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membuf_vsprintf(pChip->mbuf, fmt, ap);
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va_end(ap);
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}
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// print the fieldname, the field value, in dec & hex, and return field value
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static uint32_t
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sam3_reg_fieldname(struct sam3_chip *pChip,
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@ -1038,7 +1021,7 @@ sam3_reg_fieldname(struct sam3_chip *pChip,
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}
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// show the basics
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sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
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LOG_USER_N("\t%*s: %*d [0x%0*x] ",
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REG_NAME_WIDTH, regname,
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dwidth, v,
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hwidth, v);
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@ -1173,16 +1156,16 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
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uint32_t rcen;
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v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
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sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
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LOG_USER_N("(main xtal enabled: %s)\n",
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_yes_or_no(v));
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v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
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sam3_sprintf(pChip, "(main osc bypass: %s)\n",
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LOG_USER_N("(main osc bypass: %s)\n",
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_yes_or_no(v));
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rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
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sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
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LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
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_yes_or_no(rcen));
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v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
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sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
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LOG_USER_N("(onchip RC-OSC freq: %s)\n",
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_rc_freq[v]);
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pChip->cfg.rc_freq = 0;
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@ -1203,14 +1186,14 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
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}
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v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
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sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
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LOG_USER_N("(startup clks, time= %f uSecs)\n",
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((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
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v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
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sam3_sprintf(pChip, "(mainosc source: %s)\n",
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LOG_USER_N("(mainosc source: %s)\n",
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v ? "external xtal" : "internal RC");
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v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
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sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
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LOG_USER_N("(clock failure enabled: %s)\n",
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_yes_or_no(v));
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}
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@ -1224,19 +1207,19 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
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const char *cp;
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sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
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sam3_sprintf(pChip,"\n");
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LOG_USER_N("\n");
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v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
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sam3_sprintf(pChip, "%s\n", eproc_names[v]);
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LOG_USER_N("%s\n", eproc_names[v]);
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v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
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sam3_sprintf(pChip, "%s\n", nvpsize[v]);
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LOG_USER_N("%s\n", nvpsize[v]);
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v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
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sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
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LOG_USER_N("%s\n", nvpsize2[v]);
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v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
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sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
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LOG_USER_N("%s\n", sramsize[ v ]);
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v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
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cp = _unknown;
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@ -1247,13 +1230,13 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
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}
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}
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sam3_sprintf(pChip, "%s\n", cp);
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LOG_USER_N("%s\n", cp);
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v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
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sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
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LOG_USER_N("%s\n", nvptype[ v ]);
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v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
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sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
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LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
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}
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static void
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@ -1263,14 +1246,14 @@ sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
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v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
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sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
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LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
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v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
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v = (v * pChip->cfg.slow_freq) / 16;
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pChip->cfg.mainosc_freq = v;
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sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
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LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
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_tomhz(v),
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pChip->cfg.slow_freq / 1000,
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pChip->cfg.slow_freq % 1000);
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@ -1283,17 +1266,17 @@ sam3_explain_ckgr_plla(struct sam3_chip *pChip)
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uint32_t mula,diva;
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diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
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sam3_sprintf(pChip,"\n");
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LOG_USER_N("\n");
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mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
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sam3_sprintf(pChip,"\n");
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LOG_USER_N("\n");
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pChip->cfg.plla_freq = 0;
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if (mula == 0) {
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sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
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LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
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} else if (diva == 0) {
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sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
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LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
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} else if (diva == 1) {
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pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
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sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
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LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
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_tomhz(pChip->cfg.plla_freq));
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}
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}
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@ -1334,7 +1317,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
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break;
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}
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sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
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LOG_USER_N("%s (%3.03f Mhz)\n",
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cp,
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_tomhz(fin));
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pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
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@ -1374,14 +1357,14 @@ sam3_explain_mckr(struct sam3_chip *pChip)
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assert(0);
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break;
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}
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sam3_sprintf(pChip, "(%s)\n", cp);
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LOG_USER_N("(%s)\n", cp);
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fin = fin / pdiv;
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// sam3 has a *SINGLE* clock -
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// other at91 series parts have divisors for these.
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pChip->cfg.cpu_freq = fin;
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pChip->cfg.mclk_freq = fin;
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pChip->cfg.fclk_freq = fin;
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sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
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LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
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_tomhz(fin));
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}
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@ -1538,15 +1521,12 @@ sam3_GetInfo(struct sam3_chip *pChip)
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const struct sam3_reg_list *pReg;
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uint32_t regval;
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membuf_reset(pChip->mbuf);
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pReg = &(sam3_all_regs[0]);
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while (pReg->name) {
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// display all regs
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LOG_DEBUG("Start: %s", pReg->name);
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regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
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sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
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LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
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REG_NAME_WIDTH,
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pReg->name,
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pReg->address,
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@ -1557,14 +1537,14 @@ sam3_GetInfo(struct sam3_chip *pChip)
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LOG_DEBUG("End: %s", pReg->name);
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pReg++;
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}
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sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
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sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
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sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
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sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
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sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
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LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
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LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
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LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
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LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
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LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
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sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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pChip->cfg.unique_id[0],
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pChip->cfg.unique_id[1],
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pChip->cfg.unique_id[2],
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@ -1664,11 +1644,6 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
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// assumption is this runs at 32khz
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pChip->cfg.slow_freq = 32768;
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pChip->probed = 0;
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pChip->mbuf = membuf_new();
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if (!(pChip->mbuf)) {
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LOG_ERROR("no memory");
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return ERROR_FAIL;
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}
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}
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switch (bank->base) {
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@ -1702,11 +1677,8 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
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{
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const struct sam3_chip_details *pDetails;
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struct sam3_chip *pChip;
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void *vp;
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struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
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unsigned x;
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const char *cp;
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LOG_DEBUG("Begin");
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pDetails = all_sam3_details;
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@ -1721,16 +1693,9 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
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LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
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(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
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// Help the victim, print details about the chip
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membuf_reset(pPrivate->pChip->mbuf);
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membuf_sprintf(pPrivate->pChip->mbuf,
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"SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
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LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
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pPrivate->pChip->cfg.CHIPID_CIDR);
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sam3_explain_chipid_cidr(pPrivate->pChip);
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cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
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while (cp) {
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LOG_INFO("%s", cp);
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cp = membuf_strtok(NULL, "\n", &vp);
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}
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return ERROR_FAIL;
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}
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@ -1798,18 +1763,14 @@ _sam3_probe(struct flash_bank *bank, int noise)
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LOG_DEBUG("Here");
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r = sam3_GetInfo(pPrivate->pChip);
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if (pPrivate->pChip->probed) {
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r = sam3_GetInfo(pPrivate->pChip);
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} else {
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r = sam3_GetDetails(pPrivate);
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}
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if (r != ERROR_OK) {
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return r;
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}
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if (!(pPrivate->pChip->probed)) {
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pPrivate->pChip->probed = 1;
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LOG_DEBUG("Here");
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r = sam3_GetDetails(pPrivate);
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if (r != ERROR_OK) {
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return r;
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}
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}
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// update the flash bank size
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for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
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@ -2256,8 +2217,6 @@ sam3_write(struct flash_bank *bank,
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COMMAND_HANDLER(sam3_handle_info_command)
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{
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struct sam3_chip *pChip;
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void *vp;
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const char *cp;
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unsigned x;
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int r;
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@ -2319,13 +2278,6 @@ COMMAND_HANDLER(sam3_handle_info_command)
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return r;
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}
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// print results
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cp = membuf_strtok(pChip->mbuf, "\n", &vp);
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while (cp) {
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command_print(CMD_CTX,"%s", cp);
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cp = membuf_strtok(NULL, "\n", &vp);
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}
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return ERROR_OK;
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}
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