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Merge pull request #860 from riscv/examine_state 

target/riscv: set_dcsr_ebreak() while target->state is still changed
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Tim Newsome 2023-06-08 09:10:55 -07:00 committed by GitHub
parent c8d6ffa6f0 ad89d570e7
commit 973c72887c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 3 deletions
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6
src/target/riscv/riscv-013.c
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@ -1862,9 +1862,6 @@ static int examine(struct target *target)
return ERROR_FAIL; return ERROR_FAIL;
} }
target->state = saved_tgt_state;
target->debug_reason = saved_dbg_reason;
/* Now init registers based on what we discovered. */ /* Now init registers based on what we discovered. */
if (riscv_init_registers(target) != ERROR_OK) if (riscv_init_registers(target) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -1872,6 +1869,9 @@ static int examine(struct target *target)
if (update_dcsr(target, false) != ERROR_OK) if (update_dcsr(target, false) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
target->state = saved_tgt_state;
target->debug_reason = saved_dbg_reason;
if (!halted) { if (!halted) {
riscv013_step_or_resume_current_hart(target, false); riscv013_step_or_resume_current_hart(target, false);
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;