interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update debug_defines.h. (#711) 

This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2022-07-18 09:20:22 -07:00 committed by GitHub
parent aaf0620479
commit 969f112321
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/target/riscv/debug_defines.h
View File

@ -1,7 +1,6 @@
/* /*
* This file is auto-generated by running 'make debug_defines.h' in * This file is auto-generated by running 'make debug_defines.h' in
* https://github.com/riscv/riscv-debug-spec/ (182b9c4) * https://github.com/riscv/riscv-debug-spec/ (d749752)
* License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
*/ */
#define DTM_IDCODE 0x01 #define DTM_IDCODE 0x01
@ -313,36 +312,35 @@
* *
* When there are multiple reasons to enter Debug Mode in a single * When there are multiple reasons to enter Debug Mode in a single
* cycle, hardware should set \FcsrDcsrCause to the cause with the highest * cycle, hardware should set \FcsrDcsrCause to the cause with the highest
* priority. * priority. See table~\ref{tab:dcsrcausepriority} for priorities.
*/ */
#define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_OFFSET 6
#define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE_LENGTH 3
#define CSR_DCSR_CAUSE 0x1c0 #define CSR_DCSR_CAUSE 0x1c0
/* /*
* ebreak: An {\tt ebreak} instruction was executed. (priority 3) * ebreak: An {\tt ebreak} instruction was executed.
*/ */
#define CSR_DCSR_CAUSE_EBREAK 1 #define CSR_DCSR_CAUSE_EBREAK 1
/* /*
* trigger: A Trigger Module trigger fired with action=1. (priority 4) * trigger: A Trigger Module trigger fired with action=1.
*/ */
#define CSR_DCSR_CAUSE_TRIGGER 2 #define CSR_DCSR_CAUSE_TRIGGER 2
/* /*
* haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
* (priority 1)
*/ */
#define CSR_DCSR_CAUSE_HALTREQ 3 #define CSR_DCSR_CAUSE_HALTREQ 3
/* /*
* step: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest) * step: The hart single stepped because \FcsrDcsrStep was set.
*/ */
#define CSR_DCSR_CAUSE_STEP 4 #define CSR_DCSR_CAUSE_STEP 4
/* /*
* resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It
* is also acceptable to report 3 when this happens. (priority 2) * is also acceptable to report 3 when this happens.
*/ */
#define CSR_DCSR_CAUSE_RESETHALTREQ 5 #define CSR_DCSR_CAUSE_RESETHALTREQ 5
/* /*
* group: The hart halted because it's part of a halt group. (priority 5, * group: The hart halted because it's part of a halt group.
* highest) Harts may report 3 for this cause instead. * Harts may report 3 for this cause instead.
*/ */
#define CSR_DCSR_CAUSE_GROUP 6 #define CSR_DCSR_CAUSE_GROUP 6
/* /*