From 96924dda01b964799fc1a78524fc24d7bd2142dc Mon Sep 17 00:00:00 2001
From: Jiafei Pan <Jiafei.Pan@nxp.com>
Date: Tue, 18 Jun 2024 12:15:21 +0800
Subject: [PATCH] target: add imx8mp and evk board support

Have verified with JLink:
openocd -f interface/jlink.cfg -f board/nxp_imx8mp-evk.cfg
-c "gdb_breakpoint_override hard"

Change-Id: I74f8766b8c5334ca5758c2672c283ff2405de4c3
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8352
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/board/nxp_imx8mp-evk.cfg | 24 +++++++++++++++++
 tcl/target/imx8mp.cfg        | 52 ++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 tcl/board/nxp_imx8mp-evk.cfg
 create mode 100644 tcl/target/imx8mp.cfg

diff --git a/tcl/board/nxp_imx8mp-evk.cfg b/tcl/board/nxp_imx8mp-evk.cfg
new file mode 100644
index 000000000..4e101d454
--- /dev/null
+++ b/tcl/board/nxp_imx8mp-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP IMX8M Plus EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+
+# board has an i.MX8MP with 4 Cortex-A55 cores
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8mp.cfg]
diff --git a/tcl/target/imx8mp.cfg b/tcl/target/imx8mp.cfg
new file mode 100644
index 000000000..bddbcfd20
--- /dev/null
+++ b/tcl/target/imx8mp.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP i.MX8M Plus SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core
+}
+
+# declare the auxiliary Cortex-M7 core on AP #4
+target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0