target/riscv/riscv-011.c: fix access to non-existent register
`reg` is a number in register cache, as evident by the following call to `reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in setting cache value for another register, which does not exist, and causes a segfault if all non-existent registers are not allocated a value (`reg->value == NULL`). Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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@ -1771,10 +1771,10 @@ static riscv_error_t handle_halt_routine(struct target *target)
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reg = S0;
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reg = S0;
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break;
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break;
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case 31:
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case 31:
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reg = CSR_DPC;
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reg = GDB_REGNO_DPC;
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break;
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break;
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case 32:
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case 32:
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reg = CSR_DCSR;
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reg = GDB_REGNO_DCSR;
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break;
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break;
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default:
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default:
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assert(0);
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assert(0);
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@ -1808,8 +1808,8 @@ static riscv_error_t handle_halt_routine(struct target *target)
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}
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}
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/* TODO: get rid of those 2 variables and talk to the cache directly. */
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/* TODO: get rid of those 2 variables and talk to the cache directly. */
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info->dpc = reg_cache_get(target, CSR_DPC);
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info->dpc = reg_cache_get(target, GDB_REGNO_DPC);
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info->dcsr = reg_cache_get(target, CSR_DCSR);
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info->dcsr = reg_cache_get(target, GDB_REGNO_DCSR);
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cache_invalidate(target);
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cache_invalidate(target);
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