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Add target_write_memory wrapper: 

- replaces all calls to target->type->write_memory.
- add documentation in target_s to warn not to invoke callback directly.


git-svn-id: svn://svn.berlios.de/openocd/trunk@1960 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch 2009-05-31 09:37:57 +00:00
parent b6db182c00
commit 95e13054ca
16 changed files with 126 additions and 107 deletions
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2
src/flash/at91sam7.c
View File

@ -1027,7 +1027,7 @@ static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
/* Write one block to the PageWriteBuffer */ /* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment; buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4); wcount = CEIL(count,4);
if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK) if((retval = target_write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
{ {
return retval; return retval;
} }

132
src/flash/cfi.c
View File

@ -260,7 +260,7 @@ static void cfi_intel_clear_status_register(flash_bank_t *bank)
} }
cfi_command(bank, 0x50, command); cfi_command(bank, 0x50, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout) u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
@ -356,12 +356,12 @@ static int cfi_read_intel_pri_ext(flash_bank_t *bank)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -419,7 +419,7 @@ static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -492,7 +492,7 @@ static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I')) if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -688,13 +688,13 @@ static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
for (i = first; i <= last; i++) for (i = first; i <= last; i++)
{ {
cfi_command(bank, 0x20, command); cfi_command(bank, 0x20, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xd0, command); cfi_command(bank, 0xd0, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -704,7 +704,7 @@ static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
else else
{ {
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -715,7 +715,7 @@ static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
@ -731,37 +731,37 @@ static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
for (i = first; i <= last; i++) for (i = first; i <= last; i++)
{ {
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x80, command); cfi_command(bank, 0x80, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x30, command); cfi_command(bank, 0x30, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -771,7 +771,7 @@ static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
else else
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -782,7 +782,7 @@ static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
} }
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
static int cfi_erase(struct flash_bank_s *bank, int first, int last) static int cfi_erase(struct flash_bank_s *bank, int first, int last)
@ -842,7 +842,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
{ {
cfi_command(bank, 0x60, command); cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -850,7 +850,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
{ {
cfi_command(bank, 0x01, command); cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -860,7 +860,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
{ {
cfi_command(bank, 0xd0, command); cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -878,7 +878,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
u8 block_status; u8 block_status;
/* read block lock bit, to verify status */ /* read block lock bit, to verify status */
cfi_command(bank, 0x90, command); cfi_command(bank, 0x90, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -888,7 +888,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
{ {
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status); LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command); cfi_command(bank, 0x70, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -917,13 +917,13 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
cfi_intel_clear_status_register(bank); cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command); cfi_command(bank, 0x60, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x01, command); cfi_command(bank, 0x01, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -934,7 +934,7 @@ static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last) static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
@ -1554,12 +1554,12 @@ static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address
cfi_intel_clear_status_register(bank); cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command); cfi_command(bank, 0x40, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1567,7 +1567,7 @@ static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80) if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{ {
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1622,14 +1622,14 @@ static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordco
/* Initiate buffer operation _*/ /* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command); cfi_command(bank, 0xE8, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{ {
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1640,26 +1640,26 @@ static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordco
/* Write buffer wordcount-1 and data words */ /* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command); cfi_command(bank, bufferwsize-1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{ {
return retval; return retval;
} }
/* Commit write operation */ /* Commit write operation */
cfi_command(bank, 0xd0, command); cfi_command(bank, 0xd0, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{ {
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1680,24 +1680,24 @@ static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 addr
u8 command[8]; u8 command[8];
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xa0, command); cfi_command(bank, 0xa0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1705,7 +1705,7 @@ static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 addr
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK) if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1757,39 +1757,39 @@ static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wor
// Unlock // Unlock
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
// Buffer load command // Buffer load command
cfi_command(bank, 0x25, command); cfi_command(bank, 0x25, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
/* Write buffer wordcount-1 and data words */ /* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command); cfi_command(bank, bufferwsize-1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{ {
return retval; return retval;
} }
/* Commit write operation */ /* Commit write operation */
cfi_command(bank, 0x29, command); cfi_command(bank, 0x29, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -1797,7 +1797,7 @@ static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wor
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK) if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2012,12 +2012,12 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* return to read array mode, so we can read from flash again for padding */ /* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word); cfi_command(bank, 0xf0, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, current_word); cfi_command(bank, 0xff, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2052,12 +2052,12 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* return to read array mode */ /* return to read array mode */
cfi_command(bank, 0xf0, current_word); cfi_command(bank, 0xf0, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, current_word); cfi_command(bank, 0xff, current_word);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
} }
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param) static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
@ -2133,17 +2133,17 @@ static int cfi_probe(struct flash_bank_s *bank)
/* switch to read identifier codes mode ("AUTOSELECT") */ /* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x90, command); cfi_command(bank, 0x90, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2177,12 +2177,12 @@ static int cfi_probe(struct flash_bank_s *bank)
LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id); LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
/* switch back to read array mode */ /* switch back to read array mode */
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2203,7 +2203,7 @@ static int cfi_probe(struct flash_bank_s *bank)
* SST flashes clearly violate this, and we will consider them incompatbile for now * SST flashes clearly violate this, and we will consider them incompatbile for now
*/ */
cfi_command(bank, 0x98, command); cfi_command(bank, 0x98, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2217,12 +2217,12 @@ static int cfi_probe(struct flash_bank_s *bank)
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y')) if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{ {
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2307,12 +2307,12 @@ static int cfi_probe(struct flash_bank_s *bank)
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/ */
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2410,7 +2410,7 @@ static int cfi_intel_protect_check(struct flash_bank_s *bank)
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command); cfi_command(bank, 0x90, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2426,7 +2426,7 @@ static int cfi_intel_protect_check(struct flash_bank_s *bank)
} }
cfi_command(bank, 0xff, command); cfi_command(bank, 0xff, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
static int cfi_spansion_protect_check(struct flash_bank_s *bank) static int cfi_spansion_protect_check(struct flash_bank_s *bank)
@ -2439,19 +2439,19 @@ static int cfi_spansion_protect_check(struct flash_bank_s *bank)
int i; int i;
cfi_command(bank, 0xaa, command); cfi_command(bank, 0xaa, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x55, command); cfi_command(bank, 0x55, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
cfi_command(bank, 0x90, command); cfi_command(bank, 0x90, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK) if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2467,7 +2467,7 @@ static int cfi_spansion_protect_check(struct flash_bank_s *bank)
} }
cfi_command(bank, 0xf0, command); cfi_command(bank, 0xf0, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
} }
static int cfi_protect_check(struct flash_bank_s *bank) static int cfi_protect_check(struct flash_bank_s *bank)

2
src/flash/lpc2000.c
View File

@ -258,7 +258,7 @@ static int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u3
/* write IAP code to working area */ /* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12)); target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0)); target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
if((retval = target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK) if((retval = target_write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
{ {
return retval; return retval;
} }

2
src/flash/lpc288x.c
View File

@ -406,7 +406,7 @@ static int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
* it seems not to be a LOT slower.... * it seems not to be a LOT slower....
* bulk_write_memory() is no quicker :(*/ * bulk_write_memory() is no quicker :(*/
#if 1 #if 1
if (target->type->write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK) if (target_write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
{ {
LOG_ERROR("Write failed s %x p %x", sector, page); LOG_ERROR("Write failed s %x p %x", sector, page);
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;

4
src/flash/lpc3180_nand_controller.c
View File

@ -602,8 +602,8 @@ static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data,
/* write MLC_ECC_ENC_REG to start encode cycle */ /* write MLC_ECC_ENC_REG to start encode cycle */
target_write_u32(target, 0x200b8008, 0x0); target_write_u32(target, 0x200b8008, 0x0);
target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512)); target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6)); target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */ /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
target_write_u32(target, 0x200b8010, 0x0); target_write_u32(target, 0x200b8010, 0x0);

4
src/flash/mflash.c
View File

@ -494,7 +494,7 @@ static int mg_mflash_do_write_sects(void *buff, u32 sect_num, u32 sect_cnt,
if (ret != ERROR_OK) if (ret != ERROR_OK)
LOG_ERROR("mg_io_wait_drq time out"); LOG_ERROR("mg_io_wait_drq time out");
ret = target->type->write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr); ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
if (ret != ERROR_OK) if (ret != ERROR_OK)
LOG_ERROR("mem write error"); LOG_ERROR("mem write error");
buff_ptr += MG_MFLASH_SECTOR_SIZE; buff_ptr += MG_MFLASH_SECTOR_SIZE;
@ -927,7 +927,7 @@ static int mg_verify_interface(void)
for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++) for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++)
buff[i] = i; buff[i] = i;
target->type->write_memory(target, address, 2, target_write_memory(target, address, 2,
MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff); MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff);
memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE); memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);

4
src/flash/orion_nand.c
View File

@ -131,7 +131,7 @@ static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, i
target_buffer_set_u32(target, code_buf + i*4, code[i]); target_buffer_set_u32(target, code_buf + i*4, code[i]);
/* write code to working area */ /* write code to working area */
retval = target->type->write_memory(target, retval = target_write_memory(target,
hw->copy_area->address, hw->copy_area->address,
4, code_size/4, code_buf); 4, code_size/4, code_buf);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -143,7 +143,7 @@ static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, i
retval = target->type->bulk_write_memory(target, target_buf, retval = target->type->bulk_write_memory(target, target_buf,
size/4, data); size/4, data);
if (retval == ERROR_OK && size & 3) { if (retval == ERROR_OK && size & 3) {
retval = target->type->write_memory(target, retval = target_write_memory(target,
target_buf + (size & ~3), target_buf + (size & ~3),
1, size & 3, data + (size & ~3)); 1, size & 3, data + (size & ~3));
} }

8
src/flash/str7x.c
View File

@ -546,11 +546,11 @@ static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */ /* data word 1 */
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written); target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
bytes_written += 4; bytes_written += 4;
/* data word 2 */ /* data word 2 */
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written); target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
bytes_written += 4; bytes_written += 4;
/* start programming cycle */ /* start programming cycle */
@ -593,11 +593,11 @@ static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */ /* data word 1 */
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword); target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
bytes_written += 4; bytes_written += 4;
/* data word 2 */ /* data word 2 */
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4); target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
bytes_written += 4; bytes_written += 4;
/* start programming cycle */ /* start programming cycle */

4
src/flash/str9x.c
View File

@ -569,7 +569,7 @@ static int str9x_write(struct flash_bank_s *bank,
/* write data command */ /* write data command */
target_write_u16(target, bank_adr, 0x40); target_write_u16(target, bank_adr, 0x40);
target->type->write_memory(target, address, 2, 1, buffer + bytes_written); target_write_memory(target, address, 2, 1, buffer + bytes_written);
/* get status command */ /* get status command */
target_write_u16(target, bank_adr, 0x70); target_write_u16(target, bank_adr, 0x70);
@ -618,7 +618,7 @@ static int str9x_write(struct flash_bank_s *bank,
/* write data comamnd */ /* write data comamnd */
target_write_u16(target, bank_adr, 0x40); target_write_u16(target, bank_adr, 0x40);
target->type->write_memory(target, address, 2, 1, last_halfword); target_write_memory(target, address, 2, 1, last_halfword);
/* query status command */ /* query status command */
target_write_u16(target, bank_adr, 0x70); target_write_u16(target, bank_adr, 0x70);

10
src/target/arm7_9_common.c
View File

@ -378,7 +378,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return retval; return retval;
} }
if (current_instr==arm7_9->arm_bkpt) if (current_instr==arm7_9->arm_bkpt)
if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -392,7 +392,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return retval; return retval;
} }
if (current_instr==arm7_9->thumb_bkpt) if (current_instr==arm7_9->thumb_bkpt)
if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -2628,7 +2628,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
int i; int i;
if (!arm7_9->dcc_downloads) if (!arm7_9->dcc_downloads)
return target->type->write_memory(target, address, 4, count, buffer); return target_write_memory(target, address, 4, count, buffer);
/* regrab previously allocated working_area, or allocate a new one */ /* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area) if (!arm7_9->dcc_working_area)
@ -2639,7 +2639,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
{ {
LOG_INFO("no working area available, falling back to memory writes"); LOG_INFO("no working area available, falling back to memory writes");
return target->type->write_memory(target, address, 4, count, buffer); return target_write_memory(target, address, 4, count, buffer);
} }
/* copy target instructions to target endianness */ /* copy target instructions to target endianness */
@ -2649,7 +2649,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
} }
/* write DCC code to working area */ /* write DCC code to working area */
if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
{ {
return retval; return retval;
} }

6
src/target/cortex_m3.c
View File

@ -934,7 +934,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{ {
return retval; return retval;
} }
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -975,14 +975,14 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
/* restore original instruction (kept in target endianness) */ /* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4) if (breakpoint->length == 4)
{ {
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }
} }
else else
{ {
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }

6
src/target/feroceon.c
View File

@ -546,7 +546,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
u32 dcc_size = sizeof(dcc_code); u32 dcc_size = sizeof(dcc_code);
if (!arm7_9->dcc_downloads) if (!arm7_9->dcc_downloads)
return target->type->write_memory(target, address, 4, count, buffer); return target_write_memory(target, address, 4, count, buffer);
/* regrab previously allocated working_area, or allocate a new one */ /* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area) if (!arm7_9->dcc_working_area)
@ -557,7 +557,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
{ {
LOG_INFO("no working area available, falling back to memory writes"); LOG_INFO("no working area available, falling back to memory writes");
return target->type->write_memory(target, address, 4, count, buffer); return target_write_memory(target, address, 4, count, buffer);
} }
/* copy target instructions to target endianness */ /* copy target instructions to target endianness */
@ -565,7 +565,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */ /* write DCC code to working area */
if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) if((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
{ {
return retval; return retval;
} }

4
src/target/mips_m4k.c
View File

@ -617,7 +617,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
} }
if (current_instr == MIPS32_SDBBP) if (current_instr == MIPS32_SDBBP)
{ {
if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }
@ -635,7 +635,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (current_instr == MIPS16_SDBBP) if (current_instr == MIPS16_SDBBP)
{ {
if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }

29
src/target/target.c
View File

@ -531,6 +531,13 @@ int target_read_memory(struct target_s *target,
return target->type->read_memory(target, address, size, count, buffer); return target->type->read_memory(target, address, size, count, buffer);
} }
int target_write_memory(struct target_s *target,
u32 address, u32 size, u32 count, u8 *buffer)
{
return target->type->write_memory(target, address, size, count, buffer);
}
int target_init(struct command_context_s *cmd_ctx) int target_init(struct command_context_s *cmd_ctx)
{ {
target_t *target = all_targets; target_t *target = all_targets;
@ -898,7 +905,7 @@ int target_free_working_area_restore(struct target_s *target, working_area_t *ar
if (restore&&target->backup_working_area) if (restore&&target->backup_working_area)
{ {
int retval; int retval;
if((retval = target->type->write_memory(target, area->address, 4, area->size / 4, area->backup)) != ERROR_OK) if((retval = target_write_memory(target, area->address, 4, area->size / 4, area->backup)) != ERROR_OK)
return retval; return retval;
} }
@ -1004,7 +1011,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
if (((address % 2) == 0) && (size == 2)) if (((address % 2) == 0) && (size == 2))
{ {
return target->type->write_memory(target, address, 2, 1, buffer); return target_write_memory(target, address, 2, 1, buffer);
} }
/* handle unaligned head bytes */ /* handle unaligned head bytes */
@ -1015,7 +1022,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
if (unaligned > size) if (unaligned > size)
unaligned = size; unaligned = size;
if ((retval = target->type->write_memory(target, address, 1, unaligned, buffer)) != ERROR_OK) if ((retval = target_write_memory(target, address, 1, unaligned, buffer)) != ERROR_OK)
return retval; return retval;
buffer += unaligned; buffer += unaligned;
@ -1036,7 +1043,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
} }
else else
{ {
if ((retval = target->type->write_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK) if ((retval = target_write_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK)
return retval; return retval;
} }
@ -1048,7 +1055,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
/* handle tail writes of less than 4 bytes */ /* handle tail writes of less than 4 bytes */
if (size > 0) if (size > 0)
{ {
if ((retval = target->type->write_memory(target, address, 1, size, buffer)) != ERROR_OK) if ((retval = target_write_memory(target, address, 1, size, buffer)) != ERROR_OK)
return retval; return retval;
} }
@ -1272,7 +1279,7 @@ int target_write_u32(struct target_s *target, u32 address, u32 value)
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value); LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u32(target, value_buf, value); target_buffer_set_u32(target, value_buf, value);
if ((retval = target->type->write_memory(target, address, 4, 1, value_buf)) != ERROR_OK) if ((retval = target_write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
{ {
LOG_DEBUG("failed: %i", retval); LOG_DEBUG("failed: %i", retval);
} }
@ -1293,7 +1300,7 @@ int target_write_u16(struct target_s *target, u32 address, u16 value)
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value); LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u16(target, value_buf, value); target_buffer_set_u16(target, value_buf, value);
if ((retval = target->type->write_memory(target, address, 2, 1, value_buf)) != ERROR_OK) if ((retval = target_write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
{ {
LOG_DEBUG("failed: %i", retval); LOG_DEBUG("failed: %i", retval);
} }
@ -1312,7 +1319,7 @@ int target_write_u8(struct target_s *target, u32 address, u8 value)
LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value); LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
if ((retval = target->type->write_memory(target, address, 1, 1, &value)) != ERROR_OK) if ((retval = target_write_memory(target, address, 1, 1, &value)) != ERROR_OK)
{ {
LOG_DEBUG("failed: %i", retval); LOG_DEBUG("failed: %i", retval);
} }
@ -1967,7 +1974,7 @@ static int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char
} }
for (i=0; i<count; i++) for (i=0; i<count; i++)
{ {
int retval = target->type->write_memory(target, int retval = target_write_memory(target,
address + i * wordsize, wordsize, 1, value_buf); address + i * wordsize, wordsize, 1, value_buf);
if (ERROR_OK != retval) if (ERROR_OK != retval)
return retval; return retval;
@ -3034,7 +3041,7 @@ static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_
} }
len -= count; len -= count;
retval = target->type->write_memory(target, addr, width, count, buffer); retval = target_write_memory(target, addr, width, count, buffer);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
/* BOO !*/ /* BOO !*/
LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed", addr, width, count); LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed", addr, width, count);
@ -3525,7 +3532,7 @@ static int tcl_target_func( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
break; break;
} }
for( x = 0 ; x < c ; x++ ){ for( x = 0 ; x < c ; x++ ){
e = target->type->write_memory( target, a, b, 1, target_buf ); e = target_write_memory( target, a, b, 1, target_buf );
if( e != ERROR_OK ){ if( e != ERROR_OK ){
Jim_SetResult_sprintf( interp, "Error writing @ 0x%08x: %d\n", (int)(a), e ); Jim_SetResult_sprintf( interp, "Error writing @ 0x%08x: %d\n", (int)(a), e );
return JIM_ERR; return JIM_ERR;

12
src/target/target.h
View File

@ -167,6 +167,10 @@ typedef struct target_type_s
*/ */
int (*read_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int (*read_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int (*write_memory_imp)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int (*write_memory_imp)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
/**
* Target memory write callback. Do @b not call this function
* directly, use target_write_memory() instead.
*/
int (*write_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int (*write_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
@ -383,6 +387,14 @@ extern target_t *get_target(const char *id);
*/ */
extern int target_read_memory(struct target_s *target, extern int target_read_memory(struct target_s *target,
u32 address, u32 size, u32 count, u8 *buffer); u32 address, u32 size, u32 count, u8 *buffer);
/**
* Write @count items of @a size bytes to the memory of @a target at
* the @a address given.
*
* This routine is wrapper for target->type->write_memory.
*/
extern int target_write_memory(struct target_s *target,
u32 address, u32 size, u32 count, u8 *buffer);
extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer); extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer); extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);

4
src/target/xscale.c
View File

@ -2284,14 +2284,14 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
/* restore original instruction (kept in target endianness) */ /* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4) if (breakpoint->length == 4)
{ {
if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }
} }
else else
{ {
if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{ {
return retval; return retval;
} }