Rolf Meeser <rolfm_9dq@yahoo.de> adds flash support for NXP's LPC2900 family (ARM968E).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2715 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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doc/openocd.texi
133
doc/openocd.texi
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@ -3309,7 +3309,15 @@ and executed.
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@deffn {Flash Driver} lpc2000
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@deffn {Flash Driver} lpc2000
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Most members of the LPC1700 and LPC2000 microcontroller families from NXP
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Most members of the LPC1700 and LPC2000 microcontroller families from NXP
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include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
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include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
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@quotation Note
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There are LPC2000 devices which are not supported by the @var{lpc2000}
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driver:
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The LPC2888 is supported by the @var{lpc288x} driver.
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The LPC29xx family is supported by the @var{lpc2900} driver.
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@end quotation
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The @var{lpc2000} driver defines two mandatory and one optional parameters,
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The @var{lpc2000} driver defines two mandatory and one optional parameters,
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which must appear in the following order:
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which must appear in the following order:
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@ -3349,6 +3357,129 @@ flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
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@end example
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@end example
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@end deffn
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@end deffn
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@deffn {Flash Driver} lpc2900
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This driver supports the LPC29xx ARM968E based microcontroller family
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from NXP.
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The predefined parameters @var{base}, @var{size}, @var{chip_width} and
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@var{bus_width} of the @code{flash bank} command are ignored. Flash size and
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sector layout are auto-configured by the driver.
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The driver has one additional mandatory parameter: The CPU clock rate
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(in kHz) at the time the flash operations will take place. Most of the time this
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will not be the crystal frequency, but a higher PLL frequency. The
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@code{reset-init} event handler in the board script is usually the place where
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you start the PLL.
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The driver rejects flashless devices (currently the LPC2930).
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The EEPROM in LPC2900 devices is not mapped directly into the address space.
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It must be handled much more like NAND flash memory, and will therefore be
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handled by a separate @code{lpc2900_eeprom} driver (not yet available).
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Sector protection in terms of the LPC2900 is handled transparently. Every time a
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sector needs to be erased or programmed, it is automatically unprotected.
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What is shown as protection status in the @code{flash info} command, is
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actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
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sector from ever being erased or programmed again. As this is an irreversible
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mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
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and not by the standard @code{flash protect} command.
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Example for a 125 MHz clock frequency:
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@example
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flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
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@end example
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Some @code{lpc2900}-specific commands are defined. In the following command list,
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the @var{bank} parameter is the bank number as obtained by the
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@code{flash banks} command.
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@deffn Command {lpc2900 signature} bank
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Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
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content. This is a hardware feature of the flash block, hence the calculation is
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very fast. You may use this to verify the content of a programmed device against
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a known signature.
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Example:
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@example
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lpc2900 signature 0
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signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
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@end example
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@end deffn
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@deffn Command {lpc2900 read_custom} bank filename
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Reads the 912 bytes of customer information from the flash index sector, and
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saves it to a file in binary format.
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Example:
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@example
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lpc2900 read_custom 0 /path_to/customer_info.bin
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@end example
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@end deffn
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The index sector of the flash is a @emph{write-only} sector. It cannot be
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erased! In order to guard against unintentional write access, all following
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commands need to be preceeded by a successful call to the @code{password}
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command:
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@deffn Command {lpc2900 password} bank password
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You need to use this command right before each of the following commands:
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@code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
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@code{lpc2900 secure_jtag}.
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The password string is fixed to "I_know_what_I_am_doing".
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Example:
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@example
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lpc2900 password 0 I_know_what_I_am_doing
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Potentially dangerous operation allowed in next command!
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@end example
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@end deffn
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@deffn Command {lpc2900 write_custom} bank filename type
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Writes the content of the file into the customer info space of the flash index
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sector. The filetype can be specified with the @var{type} field. Possible values
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for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
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@var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
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contain a single section, and the contained data length must be exactly
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912 bytes.
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@quotation Attention
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This cannot be reverted! Be careful!
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@end quotation
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Example:
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@example
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lpc2900 write_custom 0 /path_to/customer_info.bin bin
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@end example
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@end deffn
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@deffn Command {lpc2900 secure_sector} bank first last
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Secures the sector range from @var{first} to @var{last} (including) against
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further program and erase operations. The sector security will be effective
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after the next power cycle.
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@quotation Attention
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This cannot be reverted! Be careful!
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@end quotation
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Secured sectors appear as @emph{protected} in the @code{flash info} command.
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Example:
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@example
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lpc2900 secure_sector 0 1 1
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flash info 0
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#0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
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# 0: 0x00000000 (0x2000 8kB) not protected
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# 1: 0x00002000 (0x2000 8kB) protected
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# 2: 0x00004000 (0x2000 8kB) not protected
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@end example
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@end deffn
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@deffn Command {lpc2900 secure_jtag} bank
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Irreversibly disable the JTAG port. The new JTAG security setting will be
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effective after the next power cycle.
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@quotation Attention
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This cannot be reverted! Be careful!
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@end quotation
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Examples:
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@example
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lpc2900 secure_jtag 0
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@end example
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@end deffn
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@end deffn
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@deffn {Flash Driver} ocl
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@deffn {Flash Driver} ocl
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@emph{No idea what this is, other than using some arm7/arm9 core.}
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@emph{No idea what this is, other than using some arm7/arm9 core.}
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@ -9,6 +9,8 @@ libflash_la_SOURCES = \
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arm_nandio.c \
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arm_nandio.c \
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flash.c \
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flash.c \
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lpc2000.c \
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lpc2000.c \
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lpc288x.c \
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lpc2900.c \
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cfi.c \
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cfi.c \
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non_cfi.c \
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non_cfi.c \
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at91sam7.c \
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at91sam7.c \
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@ -32,7 +34,6 @@ libflash_la_SOURCES = \
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s3c2412_nand.c \
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s3c2412_nand.c \
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s3c2440_nand.c \
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s3c2440_nand.c \
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s3c2443_nand.c \
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s3c2443_nand.c \
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lpc288x.c \
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ocl.c \
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ocl.c \
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mflash.c \
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mflash.c \
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pic32mx.c \
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pic32mx.c \
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@ -43,6 +44,8 @@ noinst_HEADERS = \
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arm_nandio.h \
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arm_nandio.h \
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flash.h \
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flash.h \
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lpc2000.h \
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lpc2000.h \
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lpc288x.h \
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lpc2900.h \
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cfi.h \
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cfi.h \
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non_cfi.h \
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non_cfi.h \
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at91sam7.h \
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at91sam7.h \
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@ -57,7 +60,6 @@ noinst_HEADERS = \
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tms470.h \
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tms470.h \
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s3c24xx_nand.h \
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s3c24xx_nand.h \
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s3c24xx_regs_nand.h \
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s3c24xx_regs_nand.h \
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lpc288x.h \
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mflash.h \
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mflash.h \
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ocl.h \
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ocl.h \
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pic32mx.h \
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pic32mx.h \
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@ -47,6 +47,8 @@ static int handle_flash_protect_command(struct command_context_s *cmd_ctx, char
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/* flash drivers
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/* flash drivers
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*/
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*/
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extern flash_driver_t lpc2000_flash;
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extern flash_driver_t lpc2000_flash;
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extern flash_driver_t lpc288x_flash;
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extern flash_driver_t lpc2900_flash;
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extern flash_driver_t cfi_flash;
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extern flash_driver_t cfi_flash;
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extern flash_driver_t at91sam3_flash;
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extern flash_driver_t at91sam3_flash;
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extern flash_driver_t at91sam7_flash;
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extern flash_driver_t at91sam7_flash;
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@ -58,13 +60,14 @@ extern flash_driver_t str9xpec_flash;
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extern flash_driver_t stm32x_flash;
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extern flash_driver_t stm32x_flash;
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extern flash_driver_t tms470_flash;
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extern flash_driver_t tms470_flash;
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extern flash_driver_t ecosflash_flash;
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extern flash_driver_t ecosflash_flash;
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extern flash_driver_t lpc288x_flash;
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extern flash_driver_t ocl_flash;
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extern flash_driver_t ocl_flash;
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extern flash_driver_t pic32mx_flash;
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extern flash_driver_t pic32mx_flash;
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extern flash_driver_t avr_flash;
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extern flash_driver_t avr_flash;
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flash_driver_t *flash_drivers[] = {
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flash_driver_t *flash_drivers[] = {
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&lpc2000_flash,
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&lpc2000_flash,
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&lpc288x_flash,
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&lpc2900_flash,
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&cfi_flash,
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&cfi_flash,
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&at91sam7_flash,
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&at91sam7_flash,
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&at91sam3_flash,
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&at91sam3_flash,
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@ -76,7 +79,6 @@ flash_driver_t *flash_drivers[] = {
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&stm32x_flash,
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&stm32x_flash,
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&tms470_flash,
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&tms470_flash,
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&ecosflash_flash,
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&ecosflash_flash,
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&lpc288x_flash,
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&ocl_flash,
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&ocl_flash,
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&pic32mx_flash,
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&pic32mx_flash,
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&avr_flash,
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&avr_flash,
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,27 @@
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/***************************************************************************
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* Copyright (C) 2009 by *
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* Rolf Meeser <rolfm_9dq@yahoo.de> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef lpc2900_H
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#define lpc2900_H
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#include "flash.h"
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#endif /* lpc2900_H */
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@ -0,0 +1,105 @@
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# Hitex eval board for LPC2929/LPC2939
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# http://www.hitex.com/
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# Delays on reset lines
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jtag_nsrst_delay 50
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jtag_ntrst_delay 1
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# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
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# Adaptive clocking through RTCK is not supported.
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jtag_khz 2000
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# Target device: LPC29xx with ETB
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# The following variables are used by the LPC2900 script:
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# HAS_ETB Must be set to 1. The CPU on this board has ETB.
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# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
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set HAS_ETB 1
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set FLASH_CLOCK 112000
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source [find target/lpc2900.cfg]
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# A working area will help speeding the flash programming
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#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
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$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
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# Event handlers
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$_TARGETNAME configure -event reset-start {
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# Back to the slow JTAG clock
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jtag_khz 2000
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}
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# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
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flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
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$_TARGETNAME configure -event reset-init {
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# Flash
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mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached
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# Use PLL
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mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz
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mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal
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mww 0xFFFF8028 0x00000005 # PLL: (power down)
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mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up)
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# --> f=112 MHz, fcco=224 MHz
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sleep 100
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mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
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# Increase JTAG speed
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jtag_khz 6000
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# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
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mww 0xE0001138 0x0000001F # P1.14 = D0
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mww 0xE000113C 0x0000001F # P1.15 = D1
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mww 0xE0001140 0x0000001F # P1.16 = D2
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mww 0xE0001144 0x0000001F # P1.17 = D3
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mww 0xE0001148 0x0000001F # P1.18 = D4
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mww 0xE000114C 0x0000001F # P1.19 = D5
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mww 0xE0001150 0x0000001F # P1.20 = D6
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mww 0xE0001154 0x0000001F # P1.21 = D7
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mww 0xE0001200 0x0000001F # P2.0 = D8
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mww 0xE0001204 0x0000001F # P2.1 = D9
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mww 0xE0001208 0x0000001F # P2.2 = D10
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mww 0xE000120C 0x0000001F # P2.3 = D11
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mww 0xE0001210 0x0000001F # P2.4 = D12
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mww 0xE0001214 0x0000001F # P2.5 = D13
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mww 0xE0001218 0x0000001F # P2.6 = D14
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mww 0xE000121C 0x0000001F # P2.7 = D15
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mww 0xE0001104 0x00000007 # P1.1 = A1
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mww 0xE0001108 0x00000007 # P1.2 = A2
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mww 0xE000110C 0x00000007 # P1.3 = A3
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mww 0xE0001110 0x00000007 # P1.4 = A4
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mww 0xE0001114 0x00000007 # P1.5 = A5
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mww 0xE0001118 0x00000007 # P1.6 = A6
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mww 0xE000111C 0x00000007 # P1.7 = A7
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mww 0xE0001028 0x00000007 # P0.10 = A8
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||||||
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mww 0xE000102C 0x00000007 # P0.11 = A9
|
||||||
|
mww 0xE0001030 0x00000007 # P0.12 = A10
|
||||||
|
mww 0xE0001034 0x00000007 # P0.13 = A11
|
||||||
|
mww 0xE0001038 0x00000007 # P0.14 = A12
|
||||||
|
mww 0xE000103C 0x00000007 # P0.15 = A13
|
||||||
|
mww 0xE0001048 0x00000007 # P0.18 = A14
|
||||||
|
mww 0xE000104C 0x00000007 # P0.19 = A15
|
||||||
|
mww 0xE0001050 0x00000007 # P0.20 = A16
|
||||||
|
mww 0xE0001054 0x00000007 # P0.21 = A17
|
||||||
|
mww 0xE0001058 0x00000007 # P0.22 = A18
|
||||||
|
mww 0xE000105C 0x00000007 # P0.23 = A19
|
||||||
|
mww 0xE0001238 0x00000007 # P2.14 = BLS0
|
||||||
|
mww 0xE000123C 0x00000007 # P2.15 = BLS1
|
||||||
|
mww 0xE0001300 0x00000007 # P3.0 = CS6
|
||||||
|
mww 0xE0001304 0x00000007 # P3.1 = CS7
|
||||||
|
mww 0xE0001130 0x00000007 # P1.12 = OE_N
|
||||||
|
mww 0xE0001134 0x00000007 # P1.13 = WE_N
|
||||||
|
mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1
|
||||||
|
mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0
|
||||||
|
mww 0x600000AC 0x00000005 # Bank6 WST1=5
|
||||||
|
mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1
|
||||||
|
mww 0x600000B0 0x00000006 # Bank6 WST2=6
|
||||||
|
mww 0x600000A8 0x00000002 # Bank6 IDCY=2
|
||||||
|
mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1
|
||||||
|
mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0
|
||||||
|
mww 0x600000C8 0x0000000A # Bank7 WST1=10
|
||||||
|
mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1
|
||||||
|
mww 0x600000CC 0x0000000C # Bank7 WST2=8
|
||||||
|
mww 0x600000C4 0x00000002 # Bank7 IDCY=2
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,65 @@
|
||||||
|
|
||||||
|
if { [info exists CHIPNAME] } {
|
||||||
|
set _CHIPNAME $CHIPNAME
|
||||||
|
} else {
|
||||||
|
set _CHIPNAME lpc2900
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [info exists CPUTAPID ] } {
|
||||||
|
set _CPUTAPID $CPUTAPID
|
||||||
|
} else {
|
||||||
|
set _CPUTAPID 0x0596802B
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [info exists HAS_ETB ] } {
|
||||||
|
} else {
|
||||||
|
# Set default (no ETB).
|
||||||
|
# Show a warning, because this should have been configured explicitely.
|
||||||
|
set HAS_ETB 0
|
||||||
|
# TODO warning?
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [info exists ETBTAPID ] } {
|
||||||
|
set _ETBTAPID $ETBTAPID
|
||||||
|
} else {
|
||||||
|
set _ETBTAPID 0x1B900F0F
|
||||||
|
}
|
||||||
|
|
||||||
|
# TRST and SRST both exist, and can be controlled independently
|
||||||
|
reset_config trst_and_srst separate
|
||||||
|
|
||||||
|
# Define the _TARGETNAME
|
||||||
|
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
|
||||||
|
|
||||||
|
# Include the ETB tap controller if asked for.
|
||||||
|
# Has to be done manually for newer devices (not an "old" LPC2917/2919).
|
||||||
|
if { $HAS_ETB == 1 } {
|
||||||
|
# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
|
||||||
|
set HAS_ETB 0
|
||||||
|
|
||||||
|
# Add the ETB tap controller and the ARM9 core debug tap
|
||||||
|
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
|
||||||
|
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||||
|
|
||||||
|
# Create the ".cpu" target
|
||||||
|
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
|
||||||
|
|
||||||
|
# Configure ETM and ETB
|
||||||
|
etm config $_TARGETNAME 8 normal full etb
|
||||||
|
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||||
|
|
||||||
|
} else {
|
||||||
|
# Add the ARM9 core debug tap
|
||||||
|
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||||
|
|
||||||
|
# Create the ".cpu" target
|
||||||
|
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
|
||||||
|
}
|
||||||
|
|
||||||
|
arm7_9 dbgrq enable
|
||||||
|
arm7_9 dcc_downloads enable
|
||||||
|
|
||||||
|
# Flash bank configuration:
|
||||||
|
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
|
||||||
|
# Flash base address, total flash size, and number of sectors are all configured automatically.
|
||||||
|
flash bank lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
|
||||||
Loading…
Reference in New Issue