WIP; doesn't work.
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
This commit is contained in:
Tim Newsome
parent
77802af655
commit
94e8250713
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@ -100,77 +100,6 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
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return ERROR_OK;
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}
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riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes)
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{
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riscv_addr_t addr =
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riscv_debug_buffer_addr(p->target)
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+ riscv_debug_buffer_size(p->target) * sizeof(p->debug_buffer[0])
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- p->data_count * sizeof(p->debug_buffer[0])
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- bytes;
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while (addr % bytes != 0) addr--;
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riscv_addr_t ptop =
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riscv_debug_buffer_addr(p->target)
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+ p->instruction_count * sizeof(p->debug_buffer[0]);
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if (addr <= ptop) {
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LOG_ERROR("unable to allocate %d bytes", (int)bytes);
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return RISCV_PROGRAM_ALLOC_FAIL;
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}
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p->data_count =
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+ riscv_debug_buffer_size(p->target)
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- (addr - riscv_debug_buffer_addr(p->target)) / sizeof(p->debug_buffer[0]);
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return addr;
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}
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riscv_addr_t riscv_program_alloc_x(struct riscv_program *p)
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{
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return riscv_program_alloc_data(p, p->target_xlen / 8);
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}
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riscv_addr_t riscv_program_alloc_d(struct riscv_program *p)
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{
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return riscv_program_alloc_data(p, 8);
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}
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riscv_addr_t riscv_program_alloc_w(struct riscv_program *p)
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{
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return riscv_program_alloc_data(p, 4);
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}
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riscv_addr_t riscv_program_alloc_h(struct riscv_program *p)
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{
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return riscv_program_alloc_data(p, 2);
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}
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riscv_addr_t riscv_program_alloc_b(struct riscv_program *p)
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{
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return riscv_program_alloc_data(p, 1);
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}
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riscv_insn_t riscv_program_read_ram(struct riscv_program *p, riscv_addr_t addr)
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{
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if (addr < riscv_debug_buffer_addr(p->target))
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return -1;
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if ((size_t)addr > riscv_debug_buffer_addr(p->target) + (riscv_debug_buffer_size(p->target) * sizeof(p->debug_buffer[0])))
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return -1;
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int off = (addr - riscv_debug_buffer_addr(p->target)) / sizeof(p->debug_buffer[0]);
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return p->debug_buffer[off];
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}
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void riscv_program_write_ram(struct riscv_program *p, riscv_addr_t addr, uint64_t d)
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{
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if (addr < riscv_debug_buffer_addr(p->target))
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return;
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if ((size_t)addr > riscv_debug_buffer_addr(p->target) + (riscv_debug_buffer_size(p->target) * sizeof(p->debug_buffer[0])))
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return;
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int off = (addr - riscv_debug_buffer_addr(p->target)) / sizeof(p->debug_buffer[0]);
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p->debug_buffer[off] = d;
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}
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int riscv_program_swr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno b, int offset)
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{
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p->writes_memory = 1;
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@ -60,22 +60,6 @@ int riscv_program_insert(struct riscv_program *p, riscv_insn_t i);
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* memory. */
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int riscv_program_save_to_dscratch(struct riscv_program *p, enum gdb_regno to_save);
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/* Allocates data of various sizes. Either returns the absolute physical
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* address or RISCV_PROGRAM_ALLOC_FAIL on failure. */
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riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes);
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riscv_addr_t riscv_program_alloc_x(struct riscv_program *p);
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riscv_addr_t riscv_program_alloc_d(struct riscv_program *p);
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riscv_addr_t riscv_program_alloc_w(struct riscv_program *p);
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riscv_addr_t riscv_program_alloc_h(struct riscv_program *p);
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riscv_addr_t riscv_program_alloc_b(struct riscv_program *p);
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#define RISCV_PROGRAM_ALLOC_FAIL ((riscv_addr_t)(-1))
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/* Reads a word of memory from this program's internal view of the debug RAM.
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* This is what you want to use to get data back from the program after it
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* executes. */
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riscv_insn_t riscv_program_read_ram(struct riscv_program *p, riscv_addr_t addr);
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void riscv_program_write_ram(struct riscv_program *p, riscv_addr_t a, uint64_t d);
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/* Helpers to assembly various instructions. Return 0 on success. These might
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* assembly into a multi-instruction sequence that overwrites some other
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* register, but those will be properly saved and restored. */
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@ -31,13 +31,13 @@
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static void riscv013_on_step_or_resume(struct target *target, bool step);
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static void riscv013_step_or_resume_current_hart(struct target *target, bool step);
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static riscv_addr_t riscv013_progbuf_addr(struct target *target);
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static riscv_addr_t riscv013_data_size(struct target *target);
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static riscv_addr_t riscv013_data_addr(struct target *target);
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static void riscv013_set_autoexec(struct target *target, unsigned index,
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bool enabled);
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static int riscv013_debug_buffer_register(struct target *target, riscv_addr_t addr);
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static void riscv013_clear_abstract_error(struct target *target);
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//static riscv_addr_t riscv013_progbuf_addr(struct target *target);
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//static riscv_addr_t riscv013_data_size(struct target *target);
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//static riscv_addr_t riscv013_data_addr(struct target *target);
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//static void riscv013_set_autoexec(struct target *target, unsigned index,
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//bool enabled);
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//static int riscv013_debug_buffer_register(struct target *target, riscv_addr_t addr);
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//static void riscv013_clear_abstract_error(struct target *target);
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/* Implementations of the functions in riscv_info_t. */
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static riscv_reg_t riscv013_get_register(struct target *target, int hartid, int regid);
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@ -517,6 +517,7 @@ static void dmi_write(struct target *target, uint16_t address, uint64_t value)
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}
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}
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#if 0
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static void increase_ac_busy_delay(struct target *target)
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{
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riscv013_info_t *info = get_info(target);
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@ -525,6 +526,7 @@ static void increase_ac_busy_delay(struct target *target)
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info->dtmcontrol_idle, info->dmi_busy_delay,
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info->ac_busy_delay);
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}
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#endif
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uint32_t abstract_register_size(unsigned width)
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{
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@ -769,6 +771,8 @@ static int register_write_direct(struct target *target, unsigned number,
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riscv_program_init(&program, target);
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assert(0);
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#if 0
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riscv_addr_t input = riscv_program_alloc_d(&program);
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riscv_program_write_ram(&program, input + 4, value >> 32);
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riscv_program_write_ram(&program, input, value);
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@ -794,6 +798,7 @@ static int register_write_direct(struct target *target, unsigned number,
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}
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return ERROR_OK;
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#endif
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}
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/** Actually read registers from the target right now. */
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@ -805,6 +810,22 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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if (result != ERROR_OK) {
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struct riscv_program program;
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riscv_program_init(&program, target);
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assert(0);
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assert(number != GDB_REGNO_S0);
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uint64_t s0;
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if (register_read_direct(target, &s0, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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// Write program to move data into s0.
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// Execute program.
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// Read S0
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if (register_read_direct(target, value, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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// Restore S0.
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if (register_write_direct(target, GDB_REGNO_S0, &s0) != ERROR_OK)
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return ERROR_FAIL;
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#if 0
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riscv_addr_t output = riscv_program_alloc_d(&program);
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riscv_program_write_ram(&program, output + 4, 0);
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riscv_program_write_ram(&program, output, 0);
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@ -833,6 +854,7 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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*value = 0;
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*value |= ((uint64_t)(riscv_program_read_ram(&program, output + 4))) << 32;
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*value |= riscv_program_read_ram(&program, output);
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#endif
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}
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LOG_DEBUG("[%d] reg[0x%x] = 0x%" PRIx64, riscv_current_hartid(target),
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@ -1080,77 +1102,19 @@ static int examine(struct target *target)
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r->debug_buffer_size[i] = info->progsize;
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/* Guess this is a 32-bit system, we're probing it. */
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r->xlen[i] = 32;
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/* First find the low 32 bits of the program buffer. This is
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* used to check for alignment. */
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struct riscv_program program32;
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riscv_program_init(&program32, target);
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riscv_program_csrrw(&program32, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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riscv_program_insert(&program32, auipc(GDB_REGNO_S0));
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riscv_program_insert(&program32, sw(GDB_REGNO_S0, GDB_REGNO_S0, -4));
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riscv_program_csrrw(&program32, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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riscv_program_fence(&program32);
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riscv_program_exec(&program32, target);
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riscv_addr_t progbuf_addr = dmi_read(target, DMI_PROGBUF0) - 4;
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if (get_field(dmi_read(target, DMI_ABSTRACTCS), DMI_ABSTRACTCS_CMDERR) != 0) {
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LOG_ERROR("Unable to find the address of the program buffer on hart %d", i);
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r->xlen[i] = -1;
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continue;
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}
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r->debug_buffer_addr[i] = progbuf_addr;
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/* Check to see if the core can execute 64 bit instructions.
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* In order to make this work we first need to */
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int offset = (progbuf_addr % 8 == 0) ? -4 : 0;
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/* This program uses a temporary register. If the core can not
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* execute 64 bit instruction, the original value of temporary
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* register (s0) will not be restored due to an exception.
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* So we have to save it and restore manually in that case.
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* If the core can execute 64 bit instruction, the saved value
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* is wrong, because it was read with 32 bit lw instruction,
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* but the value of s0 will be restored by the reverse swap
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* of s0 and dscratch registers. */
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uint64_t s0 = riscv_get_register(target, GDB_REGNO_S0);
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struct riscv_program program64;
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riscv_program_init(&program64, target);
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riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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riscv_program_insert(&program64, auipc(GDB_REGNO_S0));
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riscv_program_insert(&program64, sd(GDB_REGNO_S0, GDB_REGNO_S0, offset));
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riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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riscv_program_fence(&program64);
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int result = riscv_program_exec(&program64, target);
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// >>> r->xlen[i] = 32;
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uint64_t value;
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int result = register_read_abstract(target, &value, GDB_REGNO_S0, 64);
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if (result == ERROR_OK) {
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r->debug_buffer_addr[i] =
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(dmi_read(target, DMI_PROGBUF0 + (8 + offset) / 4) << 32)
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+ dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4)
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- 4;
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r->xlen[i] = 64;
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} else {
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riscv_set_register(target, GDB_REGNO_S0, s0);
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r->xlen[i] = 32;
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}
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/* Display this as early as possible to help people who are using
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* really slow simulators. */
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LOG_DEBUG(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64, i,
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r->xlen[i], r->debug_buffer_addr[i]);
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if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) {
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LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx", i,
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(long)r->debug_buffer_addr[i]);
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abort();
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}
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/* Check to see if we can use the data words as an extended
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* program buffer or not. */
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if (r->debug_buffer_addr[i] + (4 * r->debug_buffer_size[i]) == riscv013_data_addr(target)) {
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r->debug_buffer_size[i] += riscv013_data_size(target);
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LOG_DEBUG("extending the debug buffer using data words, total size %d", r->debug_buffer_size[i]);
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}
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LOG_DEBUG(" hart %d: XLEN=%d", i, r->xlen[i]);
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}
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/* Then we check the number of triggers availiable to each hart. */
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@ -1172,8 +1136,7 @@ static int examine(struct target *target)
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riscv_count_harts(target));
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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if (riscv_hart_enabled(target, i)) {
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LOG_INFO(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64
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", %d triggers", i, r->xlen[i], r->debug_buffer_addr[i],
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LOG_INFO(" hart %d: XLEN=%d, %d triggers", i, r->xlen[i],
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r->trigger_count[i]);
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} else {
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LOG_INFO(" hart %d: currently disabled", i);
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@ -1296,6 +1259,7 @@ static int deassert_reset(struct target *target)
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return ERROR_OK;
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}
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#if 0
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static void write_to_buf(uint8_t *buffer, uint64_t value, unsigned size)
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{
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switch (size) {
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@ -1316,6 +1280,7 @@ static void write_to_buf(uint8_t *buffer, uint64_t value, unsigned size)
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assert(false);
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}
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}
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#endif
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/**
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* Read the requested memory, taking care to execute every read exactly once,
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@ -1324,7 +1289,7 @@ static void write_to_buf(uint8_t *buffer, uint64_t value, unsigned size)
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static int read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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RISCV013_INFO(info);
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//RISCV013_INFO(info);
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LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
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size, address);
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@ -1342,6 +1307,8 @@ static int read_memory(struct target *target, target_addr_t address,
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struct riscv_program program;
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riscv_program_init(&program, target);
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assert(0);
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#if 0
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riscv_addr_t r_data = riscv_program_alloc_w(&program);
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riscv_addr_t r_addr = riscv_program_alloc_x(&program);
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riscv_program_fence(&program);
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@ -1496,6 +1463,7 @@ static int read_memory(struct target *target, target_addr_t address,
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riscv_addr_t addr = cur_addr - size;
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write_to_buf(buffer + addr - address, value, size);
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LOG_DEBUG("M[0x%" TARGET_PRIxADDR "] reads 0x%08x", addr, value);
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#endif
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riscv_set_register(target, GDB_REGNO_S0, s0);
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riscv_set_register(target, GDB_REGNO_S1, s1);
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@ -1505,7 +1473,7 @@ static int read_memory(struct target *target, target_addr_t address,
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static int write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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RISCV013_INFO(info);
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//RISCV013_INFO(info);
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LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
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@ -1522,6 +1490,8 @@ static int write_memory(struct target *target, target_addr_t address,
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struct riscv_program program;
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riscv_program_init(&program, target);
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assert(0);
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#if 0
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riscv_addr_t r_data = riscv_program_alloc_w(&program);
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riscv_addr_t r_addr = riscv_program_alloc_x(&program);
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riscv_program_fence(&program);
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@ -1682,6 +1652,7 @@ static int write_memory(struct target *target, target_addr_t address,
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}
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riscv013_set_autoexec(target, d_data, 0);
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#endif
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riscv_set_register(target, GDB_REGNO_S0, s0);
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riscv_set_register(target, GDB_REGNO_S1, s1);
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return ERROR_OK;
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@ -1992,13 +1963,16 @@ static void riscv013_step_or_resume_current_hart(struct target *target, bool ste
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abort();
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}
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#if 0
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riscv_addr_t riscv013_progbuf_addr(struct target *target)
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{
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RISCV013_INFO(info);
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assert(info->progbuf_addr != -1);
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return info->progbuf_addr;
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}
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#endif
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#if 0
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riscv_addr_t riscv013_data_size(struct target *target)
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{
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RISCV013_INFO(info);
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@ -2008,7 +1982,9 @@ riscv_addr_t riscv013_data_size(struct target *target)
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}
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return info->data_size;
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}
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#endif
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||||
#if 0
|
||||
riscv_addr_t riscv013_data_addr(struct target *target)
|
||||
{
|
||||
RISCV013_INFO(info);
|
||||
|
|
@ -2018,7 +1994,9 @@ riscv_addr_t riscv013_data_addr(struct target *target)
|
|||
}
|
||||
return info->data_addr;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
void riscv013_set_autoexec(struct target *target, unsigned index, bool enabled)
|
||||
{
|
||||
RISCV013_INFO(info);
|
||||
|
|
@ -2040,7 +2018,9 @@ void riscv013_set_autoexec(struct target *target, unsigned index, bool enabled)
|
|||
dmi_write(target, DMI_ABSTRACTAUTO, aa);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
int riscv013_debug_buffer_register(struct target *target, riscv_addr_t addr)
|
||||
{
|
||||
if (addr >= riscv013_data_addr(target))
|
||||
|
|
@ -2069,3 +2049,4 @@ void riscv013_clear_abstract_error(struct target *target)
|
|||
// Clear the error status.
|
||||
dmi_write(target, DMI_ABSTRACTCS, abstractcs & DMI_ABSTRACTCS_CMDERR);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1235,7 +1235,6 @@ void riscv_info_init(struct target *target, riscv_info_t *r)
|
|||
|
||||
for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
|
||||
r->xlen[h] = -1;
|
||||
r->debug_buffer_addr[h] = -1;
|
||||
|
||||
for (size_t e = 0; e < RISCV_MAX_REGISTERS; ++e)
|
||||
r->valid_saved_registers[h][e] = false;
|
||||
|
|
@ -1483,14 +1482,6 @@ size_t riscv_debug_buffer_size(struct target *target)
|
|||
return r->debug_buffer_size[riscv_current_hartid(target)];
|
||||
}
|
||||
|
||||
riscv_addr_t riscv_debug_buffer_addr(struct target *target)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
riscv_addr_t out = r->debug_buffer_addr[riscv_current_hartid(target)];
|
||||
assert((out & 3) == 0);
|
||||
return out;
|
||||
}
|
||||
|
||||
int riscv_debug_buffer_enter(struct target *target, struct riscv_program *program)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
|
|
|
|||
|
|
@ -72,9 +72,6 @@ typedef struct {
|
|||
* target controls, while otherwise only a single hart is controlled. */
|
||||
int trigger_unique_id[RISCV_MAX_HWBPS];
|
||||
|
||||
/* The address of the debug RAM buffer. */
|
||||
riscv_addr_t debug_buffer_addr[RISCV_MAX_HARTS];
|
||||
|
||||
/* The number of entries in the debug buffer. */
|
||||
int debug_buffer_size[RISCV_MAX_HARTS];
|
||||
|
||||
|
|
@ -213,7 +210,6 @@ int riscv_count_triggers_of_hart(struct target *target, int hartid);
|
|||
/* These helper functions let the generic program interface get target-specific
|
||||
* information. */
|
||||
size_t riscv_debug_buffer_size(struct target *target);
|
||||
riscv_addr_t riscv_debug_buffer_addr(struct target *target);
|
||||
|
||||
int riscv_debug_buffer_enter(struct target *target, struct riscv_program *program);
|
||||
int riscv_debug_buffer_leave(struct target *target, struct riscv_program *program);
|
||||
|
|
|
|||
Loading…
Reference in New Issue