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aarch64: support for aarch32 ARM_MODE_UND 

Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)

Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Julien Massot 2022-01-12 09:41:13 +01:00 committed by Antonio Borneo
parent 5e0cc43838
commit 93f2276cdd
2 changed files with 7 additions and 0 deletions
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3
src/target/aarch64.c
View File

@ -102,6 +102,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
case ARM_MODE_FIQ: case ARM_MODE_FIQ:
case ARM_MODE_IRQ: case ARM_MODE_IRQ:
case ARM_MODE_HYP: case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS: case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break; break;
@ -180,6 +181,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARM_MODE_FIQ: case ARM_MODE_FIQ:
case ARM_MODE_IRQ: case ARM_MODE_IRQ:
case ARM_MODE_HYP: case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS: case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break; break;
@ -1049,6 +1051,7 @@ static int aarch64_post_debug_entry(struct target *target)
case ARM_MODE_FIQ: case ARM_MODE_FIQ:
case ARM_MODE_IRQ: case ARM_MODE_IRQ:
case ARM_MODE_HYP: case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS: case ARM_MODE_SYS:
instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0); instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
break; break;

4
src/target/armv8.c
View File

@ -77,6 +77,10 @@ static const struct {
.name = "HYP", .name = "HYP",
.psr = ARM_MODE_HYP, .psr = ARM_MODE_HYP,
}, },
{
.name = "UND",
.psr = ARM_MODE_UND,
},
{ {
.name = "SYS", .name = "SYS",
.psr = ARM_MODE_SYS, .psr = ARM_MODE_SYS,