Reading/writing s1 now works.
This commit is contained in:
Tim Newsome
parent
0881092d9b
commit
90f458e63f
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@ -182,6 +182,11 @@ static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
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(dest << 7) |
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MATCH_ORI;
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}
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static uint32_t nop(void)
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{
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return addi(0, 0, 0);
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}
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*/
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static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
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@ -199,8 +204,3 @@ static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
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(dest << 7) |
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MATCH_SRLI;
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}
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static uint32_t nop(void)
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{
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return addi(0, 0, 0);
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}
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@ -330,12 +330,14 @@ static void dram_write32(struct target *target, unsigned int index, uint32_t val
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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#if 1
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if (!set_interrupt &&
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info->dram_valid & (1<<index) &&
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info->dram[index] == value) {
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LOG_DEBUG("DRAM cache hit: 0x%x @%d", value, index);
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return;
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}
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#endif
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uint64_t dbus_value = DMCONTROL_HALTNOT | value;
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if (set_interrupt)
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@ -435,6 +437,28 @@ static int wait_for_debugint_clear(struct target *target)
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}
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}
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static int wait_and_read(struct target *target, uint32_t *data, uint16_t address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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time_t start = time(NULL);
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// Throw away the results of the first read, since they'll contain the
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// result of the read that happened just before debugint was set. (Assuming
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// the last scan before calling this function was one that sets debugint.)
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dbus_read(target, info->dbus_address, address);
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while (1) {
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uint64_t dbus_value = dbus_read(target, info->dbus_address, address);
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*data = dbus_value;
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if (!get_field(dbus_value, DMCONTROL_INTERRUPT)) {
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return ERROR_OK;
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}
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if (time(NULL) - start > 2) {
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LOG_ERROR("Timed out waiting for debug int to clear.");
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return ERROR_FAIL;
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}
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}
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}
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static int read_csr(struct target *target, uint32_t *value, uint32_t csr)
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{
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dram_write32(target, 0, csrr(S0, csr), false);
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@ -534,14 +558,23 @@ static int register_get(struct reg *reg)
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{
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struct target *target = (struct target *) reg->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint32_t value = 0;
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// TODO: S0 and S1
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if (reg->number == ZERO) {
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buf_set_u64(reg->value, 0, info->xlen, 0);
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if (reg->number == S0) {
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dram_write32(target, 0, csrr(S0, CSR_DSCRATCH), false);
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dram_write32(target, 1, sw(S0, ZERO, DEBUG_RAM_START), false);
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dram_write_jump(target, 2, true);
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} else if (reg->number == S1) {
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 4 * info->dramsize - 4), false);
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dram_write32(target, 1, sw(S0, ZERO, DEBUG_RAM_START), false);
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dram_write_jump(target, 2, true);
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} else if (reg->number == ZERO) {
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buf_set_u64(reg->value, 0, info->xlen, value);
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LOG_DEBUG("%s=0x%x", reg->name, value);
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return ERROR_OK;
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} else if (reg->number <= REG_XPR31) {
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dram_write32(target, 0, sw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START), false);
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dram_write_jump(target, 1, true);
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dram_write_jump(target, 1, false);
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dram_write32(target, 0, sw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START), true);
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} else if (reg->number == REG_PC) {
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dram_write32(target, 0, csrr(S0, CSR_DPC), false);
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dram_write32(target, 1, sw(S0, ZERO, DEBUG_RAM_START), false);
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@ -558,28 +591,37 @@ static int register_get(struct reg *reg)
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return ERROR_FAIL;
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}
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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if (wait_and_read(target, &value, 0) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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uint32_t value = dram_read32(target, 0);
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LOG_DEBUG("%s=0x%x", reg->name, value);
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buf_set_u32(reg->value, 0, 32, value);
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info->dram_valid &= ~1;
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return ERROR_OK;
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}
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static int register_set(struct reg *reg, uint8_t *buf)
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{
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struct target *target = (struct target *) reg->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint32_t value = buf_get_u32(buf, 0, 32);
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LOG_DEBUG("write 0x%x to %s", value, reg->name);
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// TODO: S0 and S1
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if (reg->number <= REG_XPR31) {
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if (reg->number == S0) {
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write32(target, 1, csrw(S0, CSR_DSCRATCH), false);
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dram_write_jump(target, 2, false);
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} else if (reg->number == S1) {
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write32(target, 1, sw(S0, ZERO, DEBUG_RAM_START + 4 * info->dramsize - 4), false);
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dram_write_jump(target, 2, false);
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} else if (reg->number <= REG_XPR31) {
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dram_write32(target, 0, lw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write_jump(target, 1, false);
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} else if (reg->number == REG_PC) {
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@ -677,6 +719,53 @@ static void riscv_deinit_target(struct target *target)
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target->arch_info = NULL;
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}
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static int riscv_halt(struct target *target)
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{
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LOG_DEBUG("riscv_halt()");
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
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dram_write32(target, 1, csrr(S0, CSR_MHARTID), false);
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dram_write32(target, 2, sw(S0, ZERO, SETHALTNOT), false);
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dram_write_jump(target, 3, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static int riscv_step(struct target *target, int current, uint32_t address,
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int handle_breakpoints)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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// Hardware single step doesn't exist yet.
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#if 0
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return resume(target, current, address, handle_breakpoints, 0, true);
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#else
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uint32_t dpc;
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if (read_csr(target, &dpc, CSR_DPC) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint32_t next_pc = dpc + 4;
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// TODO: write better next pc prediction code
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if (breakpoint_add(target, next_pc, 4, BKPT_SOFT) != ERROR_OK) {
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return ERROR_FAIL;
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}
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if (resume(target, current, address, handle_breakpoints, 0, false) != ERROR_OK) {
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return ERROR_FAIL;
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}
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while (target->state == TARGET_RUNNING) {
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riscv_poll(target);
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}
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breakpoint_remove(target, next_pc);
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return ERROR_OK;
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#endif
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}
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#if 0
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static void dram_test(struct target *target)
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{
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@ -741,6 +830,22 @@ static void write_constants(struct target *target)
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}
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#endif
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#if 0
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static void test_s1(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_halt(target);
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riscv_poll(target);
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dram_write32(target, info->dramsize - 1, 0xdeadbed, false);
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dram_read32(target, info->dramsize - 1);
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riscv_step(target, true, 0, 0);
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dram_read32(target, info->dramsize - 1);
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exit(0);
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}
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#endif
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static int riscv_examine(struct target *target)
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{
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LOG_DEBUG("riscv_examine()");
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@ -789,10 +894,6 @@ static int riscv_examine(struct target *target)
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return ERROR_FAIL;
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}
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//write_constants(target);
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//light_leds(target);
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//dram_test(target);
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// Figure out XLEN.
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dram_write32(target, 0, xori(S1, ZERO, -1), false);
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// 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
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@ -816,13 +917,7 @@ static int riscv_examine(struct target *target)
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}
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// Execute.
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#if 1
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// TODO: Doesn't work without this extra nop.
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dram_write32(target, 5, nop(), false);
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dram_write_jump(target, 6, true);
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#else
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dram_write_jump(target, 5, true);
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#endif
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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@ -850,6 +945,48 @@ static int riscv_examine(struct target *target)
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target_set_examined(target);
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//write_constants(target);
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//light_leds(target);
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//dram_test(target);
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//test_s1(target);
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return ERROR_OK;
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}
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static int handle_halt(struct target *target)
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{
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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target->state = TARGET_HALTED;
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uint32_t dpc;
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if (read_csr(target, &dpc, CSR_DPC) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint32_t dcsr;
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if (read_csr(target, &dcsr, CSR_DCSR) != ERROR_OK) {
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return ERROR_FAIL;
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}
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int cause = get_field(dcsr, DCSR_CAUSE);
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switch (cause) {
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case DCSR_CAUSE_SWBP:
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case DCSR_CAUSE_HWBP:
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target->debug_reason = DBG_REASON_BREAKPOINT;
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break;
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case DCSR_CAUSE_DEBUGINT:
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target->debug_reason = DBG_REASON_DBGRQ;
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break;
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case DCSR_CAUSE_STEP:
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target->debug_reason = DBG_REASON_SINGLESTEP;
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break;
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case DCSR_CAUSE_HALT:
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default:
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LOG_ERROR("Invalid halt cause %d in DCSR (0x%x)",
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cause, dcsr);
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}
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LOG_DEBUG("halted at 0x%x", dpc);
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return ERROR_OK;
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}
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@ -863,16 +1000,8 @@ static int riscv_poll(struct target *target)
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LOG_DEBUG("debug running");
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} else if (bits.haltnot && !bits.interrupt) {
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if (target->state != TARGET_HALTED) {
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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return handle_halt(target);
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}
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target->state = TARGET_HALTED;
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uint32_t dpc;
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if (read_csr(target, &dpc, CSR_DPC) != ERROR_OK) {
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return ERROR_FAIL;
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}
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LOG_DEBUG("halted at 0x%x", dpc);
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} else if (!bits.haltnot && bits.interrupt) {
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// Target is halting. There is no state for that, so don't change anything.
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LOG_DEBUG("halting");
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@ -884,24 +1013,6 @@ static int riscv_poll(struct target *target)
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return ERROR_OK;
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}
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static int riscv_halt(struct target *target)
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{
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LOG_DEBUG("riscv_halt()");
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
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dram_write32(target, 1, csrr(S0, CSR_MHARTID), false);
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dram_write32(target, 2, sw(S0, ZERO, SETHALTNOT), false);
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dram_write_jump(target, 3, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static int riscv_resume(struct target *target, int current, uint32_t address,
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int handle_breakpoints, int debug_execution)
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{
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@ -910,13 +1021,6 @@ static int riscv_resume(struct target *target, int current, uint32_t address,
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debug_execution, false);
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}
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static int riscv_step(struct target *target, int current, uint32_t address,
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int handle_breakpoints)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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return resume(target, current, address, handle_breakpoints, 0, true);
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}
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static int riscv_assert_reset(struct target *target)
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{
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// TODO: Maybe what I implemented here is more like soft_reset_halt()?
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