target/riscv: improve register caching (riscv_write_register)
This commit introduces a new function, which can be used to reduce number of register accesses. Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov
parent
7a181e8bbc
commit
8f3a617dc7
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@ -4632,96 +4632,166 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
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}
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/**
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* This function is called when the debug user wants to change the value of a
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* register. The new value may be cached, and may not be written until the hart
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* is resumed. */
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int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
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* This function is used internally by functions that change register values.
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* If `write_through` is true, it is ensured that the value of the target's
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* register is set to be equal to the `value` argument. The cached value is
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* updated if the register is cacheable.
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*/
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static int riscv_set_or_write_register(struct target *target,
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enum gdb_regno regid, riscv_reg_t value, bool write_through)
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{
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RISCV_INFO(r);
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LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
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assert(r->set_register);
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keep_alive();
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/* TODO: Hack to deal with gdb that thinks these registers still exist. */
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if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
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riscv_supports_extension(target, 'E'))
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return ERROR_OK;
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if (!target->reg_cache) {
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assert(!target_was_examined(target));
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LOG_TARGET_DEBUG(target,
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"No cache, writing to target: %s <- 0x%" PRIx64,
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gdb_regno_name(regid), value);
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return r->set_register(target, regid, value);
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}
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struct reg *reg = &target->reg_cache->reg_list[regid];
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buf_set_u64(reg->value, 0, reg->size, value);
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struct reg *reg = get_reg_cache_entry(target, regid);
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if (gdb_regno_cacheable(regid, true)) {
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reg->valid = true;
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reg->dirty = true;
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} else {
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if (r->set_register(target, regid, value) != ERROR_OK)
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if (!reg->exist) {
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LOG_TARGET_DEBUG(target, "Register %s does not exist.", reg->name);
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return ERROR_FAIL;
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}
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LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
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target_name(target), value, reg->name, reg->valid);
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if (target->state != TARGET_HALTED) {
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LOG_TARGET_DEBUG(target,
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"Target not halted, writing to target: %s <- 0x%" PRIx64,
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reg->name, value);
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return r->set_register(target, regid, value);
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}
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const bool need_to_write = !reg->valid || reg->dirty ||
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value != buf_get_u64(reg->value, 0, reg->size);
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const bool cacheable = gdb_regno_cacheable(regid, need_to_write);
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if (!cacheable || (write_through && need_to_write)) {
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LOG_TARGET_DEBUG(target,
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"Writing to target: %s <- 0x%" PRIx64 " (cacheable=%s, valid=%s, dirty=%s)",
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reg->name, value, cacheable ? "true" : "false",
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reg->valid ? "true" : "false",
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reg->dirty ? "true" : "false");
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if (r->set_register(target, regid, value) != ERROR_OK)
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return ERROR_FAIL;
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reg->dirty = false;
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} else {
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reg->dirty = need_to_write;
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}
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buf_set_u64(reg->value, 0, reg->size, value);
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reg->valid = cacheable;
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LOG_TARGET_DEBUG(target,
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"Wrote 0x%" PRIx64 " to %s (cacheable=%s, valid=%s, dirty=%s)",
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value, reg->name, cacheable ? "true" : "false",
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reg->valid ? "true" : "false",
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reg->dirty ? "true" : "false");
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return ERROR_OK;
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}
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/**
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* This function is used to change the value of a register. The new value may
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* be cached, and may not be written until the hart is resumed.
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*/
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int riscv_set_register(struct target *target, enum gdb_regno regid,
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riscv_reg_t value)
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{
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return riscv_set_or_write_register(target, regid, value,
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/* write_through */ false);
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}
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/**
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* This function is used to change the value of a register. The new value may
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* be cached, but it will be written to hart immediately.
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*/
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int riscv_write_register(struct target *target, enum gdb_regno regid,
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riscv_reg_t value)
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{
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return riscv_set_or_write_register(target, regid, value,
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/* write_through */ true);
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}
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/**
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* This function is used to get the value of a register. If possible, the value
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* in cache will be updated.
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*/
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int riscv_get_register(struct target *target, riscv_reg_t *value,
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enum gdb_regno regid)
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{
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RISCV_INFO(r);
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assert(r->get_register);
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keep_alive();
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struct reg *reg = &target->reg_cache->reg_list[regid];
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if (!target->reg_cache) {
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assert(!target_was_examined(target));
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LOG_TARGET_DEBUG(target, "No cache, reading %s from target",
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gdb_regno_name(regid));
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return r->get_register(target, value, regid);
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}
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struct reg *reg = get_reg_cache_entry(target, regid);
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if (!reg->exist) {
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LOG_DEBUG("[%s] %s does not exist.",
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target_name(target), gdb_regno_name(regid));
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LOG_TARGET_DEBUG(target, "Register %s does not exist.", reg->name);
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return ERROR_FAIL;
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}
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if (reg && reg->valid) {
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if (reg->valid) {
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*value = buf_get_u64(reg->value, 0, reg->size);
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LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
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gdb_regno_name(regid), *value);
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LOG_TARGET_DEBUG(target, "Read %s: 0x%" PRIx64 " (cached)", reg->name,
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*value);
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return ERROR_OK;
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}
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/* TODO: Hack to deal with gdb that thinks these registers still exist. */
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if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
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riscv_supports_extension(target, 'E')) {
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*value = 0;
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return ERROR_OK;
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}
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LOG_TARGET_DEBUG(target, "Reading %s from target", reg->name);
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if (r->get_register(target, value, regid) != ERROR_OK)
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return ERROR_FAIL;
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int result = r->get_register(target, value, regid);
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if (result == ERROR_OK) {
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/* Update the cache in case we're called from
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* riscv_save_register(). */
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buf_set_u64(reg->value, 0, reg->size, *value);
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reg->valid = gdb_regno_cacheable(regid, false);
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}
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reg->valid = gdb_regno_cacheable(regid, /* is write? */ false);
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reg->dirty = false;
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LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
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gdb_regno_name(regid), *value);
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return result;
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LOG_TARGET_DEBUG(target, "Read %s: 0x%" PRIx64, reg->name, *value);
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return ERROR_OK;
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}
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/**
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* This function is used to save the value of a register in cache. The register
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* is marked as dirty, and writeback is delayed for as long as possible.
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*/
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int riscv_save_register(struct target *target, enum gdb_regno regid)
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{
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assert(target->state == TARGET_HALTED &&
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"Doesn't make sense to populate register cache on non-halted targets.");
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assert(gdb_regno_cacheable(regid, /* is write? */ false) &&
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"Only cacheable registers can be saved.");
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RISCV_INFO(r);
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riscv_reg_t value;
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if (!target->reg_cache) {
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assert(!target_was_examined(target));
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/* To create register cache it is needed to examine the target first,
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* therefore during examine, any changed register needs to be saved
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* and restored manually.
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*/
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return ERROR_OK;
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}
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struct reg *reg = &target->reg_cache->reg_list[regid];
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LOG_DEBUG("[%s] save %s", target_name(target), reg->name);
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struct reg *reg = get_reg_cache_entry(target, regid);
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LOG_TARGET_DEBUG(target, "Saving %s", reg->name);
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if (riscv_get_register(target, &value, regid) != ERROR_OK)
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return ERROR_FAIL;
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if (!reg->valid)
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return ERROR_FAIL;
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assert(reg->valid &&
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"The register is cacheable, so the cache entry must be valid now.");
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/* Mark the register dirty. We assume that this function is called
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* because the caller is about to mess with the underlying value of the
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* register. */
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@ -5080,21 +5150,34 @@ const char *gdb_regno_name(enum gdb_regno regno)
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}
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}
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/**
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* This function is the handler of user's request to read a register.
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*/
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static int register_get(struct reg *reg)
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{
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riscv_reg_info_t *reg_info = reg->arch_info;
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struct target *target = reg_info->target;
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struct target *target = ((riscv_reg_info_t *)reg->arch_info)->target;
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RISCV_INFO(r);
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/* TODO: Hack to deal with gdb that thinks these registers still exist. */
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if (reg->number > GDB_REGNO_XPR15 && reg->number <= GDB_REGNO_XPR31 &&
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riscv_supports_extension(target, 'E')) {
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buf_set_u64(reg->value, 0, reg->size, 0);
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return ERROR_OK;
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}
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if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
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if (!r->get_register_buf) {
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LOG_ERROR("Reading register %s not supported on this RISC-V target.",
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gdb_regno_name(reg->number));
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LOG_TARGET_ERROR(target,
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"Reading register %s not supported on this target.",
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reg->name);
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return ERROR_FAIL;
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}
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if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
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return ERROR_FAIL;
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reg->valid = gdb_regno_cacheable(reg->number, /* is write? */ false);
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} else {
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uint64_t value;
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int result = riscv_get_register(target, &value, reg->number);
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@ -5102,33 +5185,32 @@ static int register_get(struct reg *reg)
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return result;
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buf_set_u64(reg->value, 0, reg->size, value);
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}
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reg->valid = gdb_regno_cacheable(reg->number, false);
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char *str = buf_to_hex_str(reg->value, reg->size);
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LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
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str, reg->name, reg->valid);
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LOG_TARGET_DEBUG(target, "read 0x%s from %s (valid=%d)", str, reg->name,
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reg->valid);
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free(str);
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return ERROR_OK;
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}
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/**
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* This function is the handler of user's request to write a register.
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*/
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static int register_set(struct reg *reg, uint8_t *buf)
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{
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riscv_reg_info_t *reg_info = reg->arch_info;
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struct target *target = reg_info->target;
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struct target *target = ((riscv_reg_info_t *)reg->arch_info)->target;
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RISCV_INFO(r);
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char *str = buf_to_hex_str(buf, reg->size);
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LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
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str, reg->name, reg->valid);
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LOG_TARGET_DEBUG(target, "write 0x%s to %s (valid=%d)", str, reg->name,
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reg->valid);
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free(str);
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/* Exit early for writing x0, which on the hardware would be ignored, and we
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* don't want to update our cache. */
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if (reg->number == GDB_REGNO_ZERO)
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/* TODO: Hack to deal with gdb that thinks these registers still exist. */
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if (reg->number > GDB_REGNO_XPR15 && reg->number <= GDB_REGNO_XPR31 &&
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riscv_supports_extension(target, 'E') &&
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buf_get_u64(buf, 0, reg->size) == 0)
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return ERROR_OK;
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memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
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reg->valid = gdb_regno_cacheable(reg->number, true);
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if (reg->number == GDB_REGNO_TDATA1 ||
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reg->number == GDB_REGNO_TDATA2) {
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r->manual_hwbp_set = true;
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@ -5142,15 +5224,19 @@ static int register_set(struct reg *reg, uint8_t *buf)
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if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
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if (!r->set_register_buf) {
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LOG_ERROR("Writing register %s not supported on this RISC-V target.",
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gdb_regno_name(reg->number));
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LOG_TARGET_ERROR(target,
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"Writing register %s not supported on this target.",
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reg->name);
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return ERROR_FAIL;
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}
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if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
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if (r->set_register_buf(target, reg->number, buf) != ERROR_OK)
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return ERROR_FAIL;
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memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
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reg->valid = gdb_regno_cacheable(reg->number, /* is write? */ true);
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} else {
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uint64_t value = buf_get_u64(buf, 0, reg->size);
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const riscv_reg_t value = buf_get_u64(buf, 0, reg->size);
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if (riscv_set_register(target, reg->number, value) != ERROR_OK)
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return ERROR_FAIL;
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}
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@ -376,8 +376,16 @@ int riscv_current_hartid(const struct target *target);
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* consecutive and start with mhartid=0. */
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unsigned int riscv_count_harts(struct target *target);
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/** Set register, updating the cache. */
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/**
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* Set the register value. For cacheable registers, only the cache is updated
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* (write-back mode).
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*/
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int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
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/**
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* Set the register value and immediately write it to the target
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* (write-through mode).
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*/
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int riscv_write_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
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/** Get register, from the cache if it's in there. */
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int riscv_get_register(struct target *target, riscv_reg_t *value,
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enum gdb_regno r);
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