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- slight mips32 cleanup/reformat 

- add missing svn props

git-svn-id: svn://svn.berlios.de/openocd/trunk@1159 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-11-12 14:53:19 +00:00
parent 3a59ff8bda
commit 8f2c1659cf
6 changed files with 142 additions and 113 deletions
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158
src/target/mips32_dmaacc.c
View File

@ -49,36 +49,38 @@ static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
begin_ejtag_dma_read: begin_ejtag_dma_read:
// Setup Address /* Setup Address */
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT /* Initiate DMA Read & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data /* Read Data */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, data); mips_ejtag_drscan_32(ejtag_info, data);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read; goto begin_ejtag_dma_read;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); }
else
LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -93,42 +95,46 @@ static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
begin_ejtag_dma_read_h: begin_ejtag_dma_read_h:
// Setup Address /* Setup Address */
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT /* Initiate DMA Read & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data /* Read Data */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read_h; goto begin_ejtag_dma_read_h;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); }
else
LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
// Handle the bigendian/littleendian /* Handle the bigendian/littleendian */
if ( addr & 0x2 ) *data = (v>>16)&0xffff ; if (addr & 0x2)
else *data = (v&0x0000ffff) ; *data = (v >> 16) & 0xffff;
else
*data = (v & 0x0000ffff);
return ERROR_OK; return ERROR_OK;
} }
@ -141,45 +147,55 @@ static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
begin_ejtag_dma_read_b: begin_ejtag_dma_read_b:
// Setup Address /* Setup Address */
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Read & set DSTRT /* Initiate DMA Read & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data /* Read Data */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
goto begin_ejtag_dma_read_b; goto begin_ejtag_dma_read_b;
} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); }
else
LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
// Handle the bigendian/littleendian // Handle the bigendian/littleendian
switch(addr & 0x3) { switch (addr & 0x3) {
case 0: *data = v & 0xff; break; case 0:
case 1: *data = (v>>8) & 0xff; break; *data = v & 0xff;
case 2: *data = (v>>16) & 0xff; break; break;
case 3: *data = (v>>24) & 0xff; break; case 1:
*data = (v >> 8) & 0xff;
break;
case 2:
*data = (v >> 16) & 0xff;
break;
case 3:
*data = (v >> 24) & 0xff;
break;
} }
return ERROR_OK; return ERROR_OK;
@ -193,37 +209,39 @@ static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
begin_ejtag_dma_write: begin_ejtag_dma_write:
// Setup Address /* Setup Address */
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data /* Setup Data */
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT /* Initiate DMA Write & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write; goto begin_ejtag_dma_write;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); }
else
LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -236,44 +254,45 @@ static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
u32 ejtag_ctrl; u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
/* Handle the bigendian/littleendian */
// Handle the bigendian/littleendian
data &= 0xffff; data &= 0xffff;
data |= data<<16; data |= data << 16;
begin_ejtag_dma_write_h: begin_ejtag_dma_write_h:
// Setup Address /* Setup Address */
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data /* Setup Data */
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT /* Initiate DMA Write & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write_h; goto begin_ejtag_dma_write_h;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); }
else
LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -286,45 +305,46 @@ static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
u32 ejtag_ctrl; u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS; int retries = RETRY_ATTEMPTS;
/* Handle the bigendian/littleendian */
// Handle the bigendian/littleendian
data &= 0xff; data &= 0xff;
data |= data<<8; data |= data << 8;
data |= data<<16; data |= data << 16;
begin_ejtag_dma_write_b: begin_ejtag_dma_write_b:
// Setup Address /* Setup Address*/
v = addr; v = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Setup Data /* Setup Data */
v = data; v = data;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &v); mips_ejtag_drscan_32(ejtag_info, &v);
// Initiate DMA Write & set DSTRT /* Initiate DMA Write & set DSTRT */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear /* Wait for DSTRT to Clear */
do { do {
ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR /* Clear DMA & Check DERR */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
ejtag_ctrl = ejtag_info->ejtag_ctrl; ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR) if (ejtag_ctrl & EJTAG_CTRL_DERR)
{ {
if (retries--) { if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
goto begin_ejtag_dma_write_b; goto begin_ejtag_dma_write_b;
} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); }
else
LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
return ERROR_JTAG_DEVICE_ERROR; return ERROR_JTAG_DEVICE_ERROR;
} }
@ -351,8 +371,8 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
return retval; return retval;
} }
@ -364,8 +384,8 @@ int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
return retval; return retval;
} }
@ -377,8 +397,8 @@ int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
return retval; return retval;
} }
@ -405,8 +425,8 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
return retval; return retval;
} }
@ -418,8 +438,8 @@ int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
return retval; return retval;
} }
@ -431,8 +451,8 @@ int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *
int i; int i;
int retval; int retval;
for(i=0; i<count; i++) { for (i=0; i<count; i++) {
if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
return retval; return retval;
} }

12
src/target/mips32_pracc.c
View File

@ -234,7 +234,7 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
@ -308,7 +308,7 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
@ -387,7 +387,7 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *bu
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
@ -481,7 +481,7 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
@ -536,7 +536,7 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
@ -596,7 +596,7 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
MIPS32_SW(8,0,15), /* sw $8,($15) */ MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */ MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */ MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $10,($15) */ MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),

8
src/target/mips_ejtag.h
View File

@ -26,6 +26,7 @@
#include "types.h" #include "types.h"
#include "jtag.h" #include "jtag.h"
/* tap instructions */
#define EJTAG_INST_IDCODE 0x01 #define EJTAG_INST_IDCODE 0x01
#define EJTAG_INST_IMPCODE 0x03 #define EJTAG_INST_IMPCODE 0x03
#define EJTAG_INST_ADDRESS 0x08 #define EJTAG_INST_ADDRESS 0x08
@ -40,6 +41,7 @@
#define EJTAG_INST_TCBDATA 0x12 #define EJTAG_INST_TCBDATA 0x12
#define EJTAG_INST_BYPASS 0xFF #define EJTAG_INST_BYPASS 0xFF
/* debug control register bits */
#define EJTAG_CTRL_TOF (1 << 1) #define EJTAG_CTRL_TOF (1 << 1)
#define EJTAG_CTRL_TIF (1 << 2) #define EJTAG_CTRL_TIF (1 << 2)
#define EJTAG_CTRL_BRKST (1 << 3) #define EJTAG_CTRL_BRKST (1 << 3)
@ -85,11 +87,15 @@
#define EJTAG_DEBUG_DM (1 << 30) #define EJTAG_DEBUG_DM (1 << 30)
#define EJTAG_DEBUG_DBD (1 << 31) #define EJTAG_DEBUG_DBD (1 << 31)
/* implementaion register bits */
#define EJTAG_IMP_NODMA (1 << 14)
#define EJTAG_IMP_MIPS16 (1 << 16)
typedef struct mips_ejtag_s typedef struct mips_ejtag_s
{ {
int chain_pos; int chain_pos;
u32 impcode; u32 impcode;
// int use_dma; /*int use_dma;*/
u32 ejtag_ctrl; u32 ejtag_ctrl;
} mips_ejtag_t; } mips_ejtag_t;

11
src/target/mips_m4k.c
View File

@ -256,12 +256,15 @@ int mips_m4k_assert_reset(target_t *target)
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
} }
if (strcmp(target->variant, "ejtag_srst") == 0) { if (strcmp(target->variant, "ejtag_srst") == 0)
{
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
} else { }
else
{
/* here we should issue a srst only, but we may have to assert trst as well */ /* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST) if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{ {
@ -522,7 +525,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
case 2: case 2:
case 1: case 1:
/* if noDMA off, use DMAACC mode for memory read */ /* if noDMA off, use DMAACC mode for memory read */
if(ejtag_info->impcode & (1<<14)) if(ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer); return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
else else
return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer); return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
@ -561,7 +564,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
case 2: case 2:
case 1: case 1:
/* if noDMA off, use DMAACC mode for memory write */ /* if noDMA off, use DMAACC mode for memory write */
if(ejtag_info->impcode & (1<<14)) if(ejtag_info->impcode & EJTAG_IMP_NODMA)
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
else else
mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);