diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index b4473c30a..440ca49d1 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -65,6 +65,28 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
 	ARMV7M_XPSR,
 };
 
+static struct reg_data_type_bitfield armv8m_vpr_bits[] = {
+	{  0, 15, REG_TYPE_UINT },
+	{ 16, 19, REG_TYPE_UINT },
+	{ 20, 23, REG_TYPE_UINT },
+};
+
+static struct reg_data_type_flags_field armv8m_vpr_fields[] = {
+	{ "P0",     armv8m_vpr_bits + 0, armv8m_vpr_fields + 1, },
+	{ "MASK01", armv8m_vpr_bits + 1, armv8m_vpr_fields + 2, },
+	{ "MASK23", armv8m_vpr_bits + 2, NULL },
+};
+
+static struct reg_data_type_flags armv8m_vpr_flags[] = {
+	{ 4, armv8m_vpr_fields },
+};
+
+static struct reg_data_type armv8m_flags_vpr[] = {
+	{ REG_TYPE_ARCH_DEFINED, "vpr_reg", REG_TYPE_CLASS_FLAGS,
+		{ .reg_type_flags = armv8m_vpr_flags },
+	},
+};
+
 /*
  * These registers are not memory-mapped.  The ARMv7-M profile includes
  * memory mapped registers too, such as for the NVIC (interrupt controller)
@@ -158,6 +180,8 @@ static const struct {
 	{ ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp", NULL, },
 
 	{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp", NULL, },
+
+	{ ARMV8M_VPR, "vpr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.m-profile-mve", armv8m_flags_vpr, },
 };
 
 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
@@ -273,6 +297,9 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
 	case ARMV7M_FPSCR:
 		return ARMV7M_REGSEL_FPSCR;
 
+	case ARMV8M_VPR:
+		return ARMV8M_REGSEL_VPR;
+
 	case ARMV7M_D0 ... ARMV7M_D15:
 		return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0);
 
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 2878dd1c7..86c45f7f2 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -62,6 +62,7 @@ enum {
 	ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
 	ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
 	ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
+	ARMV8M_REGSEL_VPR = 0x24,
 	ARMV7M_REGSEL_FPSCR = 0x21,
 
 	/* 32bit Floating-point registers */
@@ -196,12 +197,15 @@ enum {
 	/* Floating-point status register */
 	ARMV7M_FPSCR,
 
+	/* Vector Predication Status and Control Register */
+	ARMV8M_VPR,
+
 	/* for convenience add registers' block delimiters */
 	ARMV7M_LAST_REG,
 	ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
 	ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
 	ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
-	ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
+	ARMV7M_FPU_LAST_REG = ARMV8M_VPR,
 	ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
 	ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
 };
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fa95fcbc7..2cea203a2 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2708,6 +2708,10 @@ int cortex_m_examine(struct target *target)
 			for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
+		/* TODO: MVE can be present without floating points. Revisit this test */
+		if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != FPV5_MVE_I)
+			armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = false;
+
 		if (!cortex_m_has_tz(target))
 			for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;