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riscv: Correct reading SPI Flash ID

This commit is contained in:
Megan Wachs 2016-11-07 20:42:43 -08:00
parent 05b12c5c20
commit 8de4ab011d
1 changed files with 36 additions and 16 deletions
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44
src/flash/nor/fespi.c
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@ -185,18 +185,14 @@ FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
return ERROR_OK; return ERROR_OK;
} }
//!!! TODO: Clean up the use of this function. static int fespi_set_dir (struct flash_bank * bank, bool dir) {
// Should just change the direction for this file's use.
static int fespi_fmt (struct flash_bank * bank, bool dir) {
struct target *target = bank->target; struct target *target = bank->target;
struct fespi_flash_bank *fespi_info = bank->driver_priv; struct fespi_flash_bank *fespi_info = bank->driver_priv;
uint32_t ctrl_base = fespi_info->ctrl_base; uint32_t ctrl_base = fespi_info->ctrl_base;
FESPI_WRITE_REG(FESPI_REG_FMT, FESPI_WRITE_REG(FESPI_REG_FMT,
FESPI_FMT_PROTO(FESPI_PROTO_S) | (FESPI_READ_REG(FESPI_REG_FMT) & ~(FESPI_FMT_DIR(0xFFFFFFFF))) |
FESPI_FMT_PROTO(FESPI_ENDIAN_MSB) | FESPI_FMT_DIR(dir));
FESPI_FMT_DIR(dir) |
FESPI_FMT_LEN(8));
return ERROR_OK; return ERROR_OK;
@ -246,7 +242,7 @@ static int fespi_wip (struct flash_bank * bank, int timeout) {
int64_t endtime; int64_t endtime;
fespi_fmt(bank, FESPI_DIR_RX); fespi_set_dir(bank, FESPI_DIR_RX);
FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_HOLD); FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
endtime = timeval_ms() + timeout; endtime = timeval_ms() + timeout;
@ -256,15 +252,15 @@ static int fespi_wip (struct flash_bank * bank, int timeout) {
do { do {
alive_sleep(1);
fespi_tx(bank, 0); fespi_tx(bank, 0);
if ((fespi_rx(bank) & SPIFLASH_BSY_BIT) == 0) { if ((fespi_rx(bank) & SPIFLASH_BSY_BIT) == 0) {
FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_AUTO); FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
fespi_fmt(bank, FESPI_DIR_TX); fespi_set_dir(bank, FESPI_DIR_TX);
return ERROR_OK; return ERROR_OK;
} }
alive_sleep(1);
} while (timeval_ms() < endtime); } while (timeval_ms() < endtime);
LOG_ERROR("timeout"); LOG_ERROR("timeout");
@ -498,11 +494,28 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
fespi_set_dir(bank, FESPI_DIR_RX);
/* Send SPI command "read ID" */ /* Send SPI command "read ID" */
FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
fespi_tx(bank, SPIFLASH_READ_ID); fespi_tx(bank, SPIFLASH_READ_ID);
/* Send dummy bytes to actually read the ID.*/
fespi_tx(bank, 0);
fespi_tx(bank, 0);
fespi_tx(bank, 0);
/* read ID from Receive Register */ /* read ID from Receive Register */
*id = fespi_rx(bank) & 0x00ffffff; *id = 0;
fespi_rx(bank);
*id = fespi_rx(bank);
*id |= (fespi_rx(bank) << 8);
*id |= (fespi_rx(bank) << 16);
FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
fespi_set_dir(bank, FESPI_DIR_TX);
return ERROR_OK; return ERROR_OK;
} }
@ -536,6 +549,13 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
target_device->name, bank->base); target_device->name, bank->base);
/* read and decode flash ID; returns in SW mode */ /* read and decode flash ID; returns in SW mode */
// TODO!!! Pass these arguments in to the driver
// Elsewhere this driver assumes these are set this way,
// but should really save and restore at the entry points.
FESPI_WRITE_REG(FESPI_REG_SCKDIV, 3);
FESPI_WRITE_REG(FESPI_REG_TXCTRL, FESPI_TXWM(1));
fespi_set_dir(bank, FESPI_DIR_TX);
retval = fespi_read_flash_id(bank, &id); retval = fespi_read_flash_id(bank, &id);
FESPI_ENABLE_HW_MODE(); FESPI_ENABLE_HW_MODE();