From 3abb347bd914242b9396bfc96d9781163b42c391 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 15 Jun 2017 14:43:15 -0700 Subject: [PATCH 1/5] Tighten up debug output. Assuming the program allocating code works, we don't need its output. Only output parts of the debug RAM that are actually doing something. --- src/target/riscv/program.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/src/target/riscv/program.c b/src/target/riscv/program.c index 6f7b10bb5..04edf6a09 100644 --- a/src/target/riscv/program.c +++ b/src/target/riscv/program.c @@ -17,8 +17,6 @@ int riscv_program_lal(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad /* Program interface. */ int riscv_program_init(struct riscv_program *p, struct target *target) { - LOG_DEBUG("riscv_program_init: p=%p", p); - memset(p, 0, sizeof(*p)); p->target = target; p->instruction_count = 0; @@ -72,14 +70,19 @@ int riscv_program_exec(struct riscv_program *p, struct target *t) return ERROR_FAIL; } - for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i) { - LOG_DEBUG("Executing program %p: debug_buffer[%02x] = DASM(0x%08lx)", p, (int)i, (long)p->debug_buffer[i]); - if (i <= p->instruction_count || i >= riscv_debug_buffer_size(p->target) - p->data_count) + for (unsigned i = 0; i < riscv_debug_buffer_size(p->target); ++i) { + if (i < p->instruction_count) { + LOG_DEBUG("%p: debug_buffer[%02x] = DASM(0x%08x)", p, i, p->debug_buffer[i]); riscv_write_debug_buffer(t, i, p->debug_buffer[i]); + } + if (i >= riscv_debug_buffer_size(p->target) - p->data_count) { + LOG_DEBUG("%p: debug_buffer[%02x] = 0x%08x", p, i, p->debug_buffer[i]); + riscv_write_debug_buffer(t, i, p->debug_buffer[i]); + } } if (riscv_execute_debug_buffer(t) != ERROR_OK) { - LOG_DEBUG("Unable to execute program %p", p); + LOG_ERROR("Unable to execute program %p", p); return ERROR_FAIL; } @@ -96,8 +99,6 @@ int riscv_program_exec(struct riscv_program *p, struct target *t) riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes) { - LOG_DEBUG("allocating %d bytes of data", (int)bytes); - riscv_addr_t addr = riscv_debug_buffer_addr(p->target) + riscv_debug_buffer_size(p->target) * sizeof(p->debug_buffer[0]) @@ -110,11 +111,10 @@ riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes) + p->instruction_count * sizeof(p->debug_buffer[0]); if (addr <= ptop) { - LOG_DEBUG("unable to allocate %d bytes", (int)bytes); + LOG_ERROR("unable to allocate %d bytes", (int)bytes); return RISCV_PROGRAM_ALLOC_FAIL; } - LOG_DEBUG("allocated %d bytes at 0x%08lx", (int)bytes, (long)addr); p->data_count = + riscv_debug_buffer_size(p->target) - (addr - riscv_debug_buffer_addr(p->target)) / sizeof(p->debug_buffer[0]); @@ -474,17 +474,14 @@ int riscv_program_lal(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad int riscv_program_insert(struct riscv_program *p, riscv_insn_t i) { - LOG_DEBUG("instruction_count: %d (p=%p)", (int)p->instruction_count, p); - if (p->instruction_count + p->data_count + 1 > riscv_debug_buffer_size(p->target)) { - LOG_DEBUG("Unable to insert instruction:"); - LOG_DEBUG(" instruction_count=%d", (int)p->instruction_count); - LOG_DEBUG(" data_count =%d", (int)p->data_count); - LOG_DEBUG(" buffer size =%d", (int)riscv_debug_buffer_size(p->target)); + LOG_ERROR("Unable to insert instruction:"); + LOG_ERROR(" instruction_count=%d", (int)p->instruction_count); + LOG_ERROR(" data_count =%d", (int)p->data_count); + LOG_ERROR(" buffer size =%d", (int)riscv_debug_buffer_size(p->target)); return ERROR_FAIL; } - LOG_DEBUG("PROGBUF[%d] = DASM(0x%08x) [0x%08x]", (int)p->instruction_count, i, i); p->debug_buffer[p->instruction_count] = i; p->instruction_count++; return ERROR_OK; From 851849a29582f789d886ed30a9f0f60bb1cfd52e Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 15 Jun 2017 15:18:42 -0700 Subject: [PATCH 2/5] Tell the user about detected harts. --- src/target/riscv/riscv-013.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index fa240dfb4..d5297260c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1097,15 +1097,12 @@ static int examine(struct target *target) r->xlen[i] = 64; } - LOG_DEBUG("hart %d has XLEN=%d", i, r->xlen[i]); - LOG_DEBUG("found program buffer at 0x%08lx", (long)(r->debug_buffer_addr[i])); - if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) { LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i, (long)r->debug_buffer_addr[i]); abort(); } - + /* Check to see if we can use the data words as an extended * program buffer or not. */ if (r->debug_buffer_addr[i] + (4 * r->debug_buffer_size[i]) == riscv013_data_addr(target)) { @@ -1132,10 +1129,15 @@ static int examine(struct target *target) riscv_resume_all_harts(target); target_set_examined(target); - // This print is used by some regression suites to know when - // they can connect with gdb/telnet. - // We will need to update those suites if we want to remove this line. - LOG_INFO("Examined RISC-V core"); + // Some regression suites rely on seeing 'Examined RISC-V core' to know + // when they can connect with gdb/telnet. + // We will need to update those suites if we want to change that text. + LOG_INFO("Examined RISC-V core; found %d harts", + riscv_count_harts(target)); + for (int i = 0; i < riscv_count_harts(target); ++i) { + LOG_INFO(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64, i, + r->xlen[i], r->debug_buffer_addr[i]); + } return ERROR_OK; } From fd81f7fcac9b62d9c40d690d00e43928e8731b79 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 16 Jun 2017 09:28:08 -0700 Subject: [PATCH 3/5] Fix comment. --- src/target/riscv/riscv-013.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d5297260c..abad44689 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1895,7 +1895,7 @@ static void riscv013_step_or_resume_current_hart(struct target *target, bool ste if (riscv_program_exec(&program, target) != ERROR_OK) abort(); - /* Issue the halt command, and then wait for the current hart to halt. */ + /* Issue the resume command, and then wait for the current hart to resume. */ uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL); dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1); dmi_write(target, DMI_DMCONTROL, dmcontrol); From 6082f35a5587d110d4bcf2c540d1ffa55db4ab63 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 16 Jun 2017 14:01:08 -0700 Subject: [PATCH 4/5] Update debug_defines. Clarify debug output. Update debug_defines from the spec, commit 920ec9a690. Decode dmstatus scans in the debug output. --- src/target/riscv/debug_defines.h | 108 +++++++++++++++++-------------- src/target/riscv/riscv-013.c | 62 +++++++++++++++++- 2 files changed, 118 insertions(+), 52 deletions(-) diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 2fb541b8e..e5f929105 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -84,7 +84,7 @@ /* * 0: Version described in spec version 0.11. * -* 1: Version described in spec version 0.12 (and later?), which +* 1: Version described in spec version 0.13 (and later?), which * reduces the DMI data width to 32 bits. * * Other values are reserved for future use. @@ -110,7 +110,12 @@ /* * When the debugger writes this field, it has the following meaning: * -* 0: Ignore \Fdata. (nop) +* 0: Ignore \Fdata and \Faddress. (nop) +* +* Don't send anything over the DMI during Update-DR. +* This operation should never result in a busy or error response. +* The address and data reported in the following Capture-DR +* are undefined. * * 1: Read from \Faddress. (read) * @@ -151,13 +156,11 @@ /* * 0: There is no external debug support. * -* 1: External debug support exists as it is described in this document. -* -* Other values are reserved for future standards. +* 4: External debug support exists as it is described in this document. */ -#define CSR_DCSR_XDEBUGVER_OFFSET 30 -#define CSR_DCSR_XDEBUGVER_LENGTH 2 -#define CSR_DCSR_XDEBUGVER (0x3 << CSR_DCSR_XDEBUGVER_OFFSET) +#define CSR_DCSR_XDEBUGVER_OFFSET 28 +#define CSR_DCSR_XDEBUGVER_LENGTH 4 +#define CSR_DCSR_XDEBUGVER (0xf << CSR_DCSR_XDEBUGVER_OFFSET) /* * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode. */ @@ -230,8 +233,11 @@ #define CSR_DCSR_CAUSE (0x7 << CSR_DCSR_CAUSE_OFFSET) /* * When set and not in Debug Mode, the hart will only execute a single -* instruction, and then enter Debug Mode. Interrupts are disabled -* when this bit is set. +* instruction and then enter Debug Mode. +* Interrupts are disabled when this bit is set. +* If the instruction does not complete due to an exception, +* the hart will immediately enter Debug Mode before executing +* the trap handler, with appropriate exception registers set. */ #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 @@ -255,16 +261,6 @@ #define CSR_DPC_DPC (((1L< %s", + out_text, in_text); + } } static riscv013_info_t *get_info(const struct target *target) @@ -985,9 +1043,9 @@ static int examine(struct target *target) uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL); uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS); - if (get_field(dmstatus, DMI_DMSTATUS_VERSIONLO) != 2) { + if (get_field(dmstatus, DMI_DMSTATUS_VERSION) != 2) { LOG_ERROR("OpenOCD only supports Debug Module version 2, not %d " - "(dmstatus=0x%x)", get_field(dmstatus, DMI_DMSTATUS_VERSIONLO), dmstatus); + "(dmstatus=0x%x)", get_field(dmstatus, DMI_DMSTATUS_VERSION), dmstatus); return ERROR_FAIL; } From 4d264b35790f7edaca01f2b2e38664f123138d0d Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 19 Jun 2017 08:46:02 -0700 Subject: [PATCH 5/5] Put early DEBUG notice of XLEN back. --- src/target/riscv/riscv-013.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 21363c94a..f1d4cfbf5 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1155,6 +1155,11 @@ static int examine(struct target *target) r->xlen[i] = 64; } + /* Display this as early as possible to help people who are using + * really slow simulators. */ + LOG_DEBUG(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64, i, + r->xlen[i], r->debug_buffer_addr[i]); + if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) { LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i, (long)r->debug_buffer_addr[i]);