David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle a bunch of 32-bit instructions: A5.3.4 Branches and miscellaneous control Note that this shifts some responsabililty out of helper functions, making the code and layout simpler for 32-bit decoders: they only need to know how to format the instruction and its parameters. Also, technical note: with this patch, Thumb1 decoders could now call the Thumb2 decoder if they wanted to get nicer treatment of the exiting 32-bit B/BLX instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch
parent
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8b89224c6e
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@ -2292,6 +2292,247 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *
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return -1;
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return -1;
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}
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}
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static int t2ev_b_bl(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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unsigned offset;
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unsigned b21 = 1 << 21;
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unsigned b22 = 1 << 22;
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/* instead of combining two smaller 16-bit branch instructions,
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* Thumb2 uses only one larger 32-bit instruction.
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*/
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offset = opcode & 0x7ff;
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offset |= (opcode & 0x03ff0000) >> 5;
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if (opcode & (1 << 26)) {
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offset |= 0xff << 23;
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if ((opcode & (1 << 11)) == 0)
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b21 = 0;
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if ((opcode & (1 << 13)) == 0)
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b22 = 0;
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} else {
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if (opcode & (1 << 11))
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b21 = 0;
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if (opcode & (1 << 13))
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b22 = 0;
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}
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offset |= b21;
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offset |= b22;
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address += 4;
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address += offset << 1;
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instruction->type = (opcode & (1 << 14)) ? ARM_BL : ARM_B;
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instruction->info.b_bl_bx_blx.reg_operand = -1;
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instruction->info.b_bl_bx_blx.target_address = address;
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sprintf(cp, "%s\t%#8.8" PRIx32,
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(opcode & (1 << 14)) ? "BL" : "B.W",
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address);
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return ERROR_OK;
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}
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static int t2ev_cond_b(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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unsigned offset;
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unsigned b17 = 1 << 17;
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unsigned b18 = 1 << 18;
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unsigned cond = (opcode >> 22) & 0x0f;
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offset = opcode & 0x7ff;
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offset |= (opcode & 0x003f0000) >> 5;
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if (opcode & (1 << 26)) {
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offset |= 0xffff << 19;
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if ((opcode & (1 << 11)) == 0)
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b17 = 0;
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if ((opcode & (1 << 13)) == 0)
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b18 = 0;
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} else {
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if (opcode & (1 << 11))
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b17 = 0;
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if (opcode & (1 << 13))
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b18 = 0;
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}
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offset |= b17;
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offset |= b18;
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address += 4;
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address += offset << 1;
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instruction->type = ARM_B;
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instruction->info.b_bl_bx_blx.reg_operand = -1;
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instruction->info.b_bl_bx_blx.target_address = address;
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sprintf(cp, "B%s.W\t%#8.8" PRIx32,
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arm_condition_strings[cond],
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address);
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return ERROR_OK;
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}
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static const char *special_name(int number)
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{
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char *special = "(RESERVED)";
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switch (number) {
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case 0:
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special = "apsr";
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break;
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case 1:
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special = "iapsr";
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break;
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case 2:
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special = "eapsr";
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break;
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case 3:
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special = "xpsr";
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break;
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case 5:
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special = "ipsr";
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break;
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case 6:
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special = "epsr";
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break;
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case 7:
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special = "iepsr";
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break;
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case 8:
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special = "msp";
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break;
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case 9:
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special = "psp";
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break;
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case 16:
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special = "primask";
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break;
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case 17:
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special = "basepri";
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break;
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case 18:
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special = "basepri_max";
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break;
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case 19:
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special = "faultmask";
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break;
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case 20:
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special = "control";
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break;
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}
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return special;
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}
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static int t2ev_hint(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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const char *mnemonic;
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if (opcode & 0x0700) {
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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strcpy(cp, "UNDEFINED");
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return ERROR_OK;
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}
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if (opcode & 0x00f0) {
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sprintf(cp, "DBG\t#%d", opcode & 0xf);
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return ERROR_OK;
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}
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switch (opcode & 0x0f) {
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case 0:
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mnemonic = "NOP.W";
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break;
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case 1:
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mnemonic = "YIELD.W";
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break;
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case 2:
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mnemonic = "WFE.W";
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break;
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case 3:
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mnemonic = "WFI.W";
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break;
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case 4:
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mnemonic = "SEV.W";
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break;
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default:
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mnemonic = "HINT.W (UNRECOGNIZED)";
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break;
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}
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strcpy(cp, mnemonic);
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return ERROR_OK;
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}
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static int t2ev_misc(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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const char *mnemonic;
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switch ((opcode >> 4) & 0x0f) {
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case 2:
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mnemonic = "CLREX";
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break;
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case 4:
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mnemonic = "DSB";
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break;
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case 5:
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mnemonic = "DMB";
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break;
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case 6:
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mnemonic = "ISB";
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break;
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default:
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return ERROR_INVALID_ARGUMENTS;
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}
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strcpy(cp, mnemonic);
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return ERROR_OK;
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}
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static int t2ev_b_misc(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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/* permanently undefined */
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if ((opcode & 0x07f07000) == 0x07f02000) {
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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strcpy(cp, "UNDEFINED");
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return ERROR_OK;
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}
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switch ((opcode >> 12) & 0x5) {
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case 0x1:
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case 0x5:
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return t2ev_b_bl(opcode, address, instruction, cp);
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case 0x4:
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goto undef;
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case 0:
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if (((opcode >> 23) & 0x07) == 0x07)
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return t2ev_cond_b(opcode, address, instruction, cp);
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if (opcode & (1 << 26))
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goto undef;
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break;
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}
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switch ((opcode >> 20) & 0x7f) {
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case 0x38:
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case 0x39:
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sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff),
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(opcode >> 16) & 0x0f);
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return ERROR_OK;
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case 0x3a:
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return t2ev_hint(opcode, address, instruction, cp);
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case 0x3b:
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return t2ev_misc(opcode, address, instruction, cp);
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case 0x3e:
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case 0x3f:
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sprintf(cp, "MRS\tr%d, %s", (opcode >> 16) & 0x0f,
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special_name(opcode & 0xff));
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return ERROR_OK;
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}
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undef:
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return ERROR_INVALID_ARGUMENTS;
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}
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/*
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/*
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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* always set. That means eventual arm_simulate_step() support for Thumb2
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* always set. That means eventual arm_simulate_step() support for Thumb2
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@ -2302,6 +2543,7 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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int retval;
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int retval;
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uint16_t op;
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uint16_t op;
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uint32_t opcode;
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uint32_t opcode;
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char *cp;
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/* clear low bit ... it's set on function pointers */
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/* clear low bit ... it's set on function pointers */
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address &= ~1;
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address &= ~1;
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@ -2332,13 +2574,30 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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return thumb_evaluate_opcode(op, address, instruction);
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return thumb_evaluate_opcode(op, address, instruction);
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}
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}
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/* FIXME decode the 32-bit instructions */
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%8.8" PRIx32 "\t",
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address, opcode);
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cp = strchr(instruction->text, 0);
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retval = ERROR_FAIL;
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/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
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if ((opcode & 0x18008000) == 0x10008000)
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retval = t2ev_b_misc(opcode, address, instruction, cp);
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/* FIXME decode more 32-bit instructions */
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if (retval == ERROR_OK)
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return retval;
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if (retval == ERROR_INVALID_ARGUMENTS) {
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instruction->type = ARM_UNDEFINED_INSTRUCTION;
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strcpy(cp, "UNDEFINED OPCODE");
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return ERROR_OK;
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}
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LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
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LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
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snprintf(instruction->text, 128,
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strcpy(cp, "(32-bit Thumb2 ...)");
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"0x%8.8" PRIx32 " 0x%8.8x\t... 32-bit Thumb2 ...",
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address, opcode);
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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