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David Brownell <david-b@pacbell.net> 

Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.

(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic.  MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2679 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-09-09 06:27:47 +00:00
parent 857c06ca8b
commit 8b2b0071a9
1 changed files with 14 additions and 4 deletions
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18
doc/openocd.texi
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@ -5038,8 +5038,13 @@ Without arguments, the current settings are displayed.
@subsection ARM11 specific commands
@cindex ARM11
@deffn Command {arm11 mcr} p1 p2 p3 p4 p5
Read coprocessor register
@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
Write @var{value} to a coprocessor @var{pX} register
passing parameters @var{CRn},
@var{CRm}, opcodes @var{opc1} and @var{opc2},
and the MCR instruction.
(The difference beween this and the MCR2 instruction is
one bit in the encoding, effecively a fifth parameter.)
@end deffn
@deffn Command {arm11 memwrite burst} [value]
@ -5054,8 +5059,13 @@ which is enabled by default.
If @var{value} is defined, first assigns that.
@end deffn
@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
Write coprocessor register
@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
Read a coprocessor @var{pX} register passing parameters @var{CRn},
@var{CRm}, opcodes @var{opc1} and @var{opc2},
and the MRC instruction.
(The difference beween this and the MRC2 instruction is
one bit in the encoding, effecively a fifth parameter.)
Displays the result.
@end deffn
@deffn Command {arm11 no_increment} [value]