stlink: Set speed before entering JTAG/SWD mode
Some boards require a slower clock speed because of passive components on the JTAG/SWD lines. The previous implementation would first try to discover the chips on the default speed, and only after discovery switch to the requested adapter_khz speed. This patch moves the speed change to just before entering the SWD/JTAG mode, which should alleviate this problem. Tested on an STLink V2 clone. Change-Id: I9734452dcc8bb28d6629e64d9a7e32ef92868cf9 Signed-off-by: Frans-Willem Hardijzer <fw@hardijzer.nl> Reviewed-on: http://openocd.zylin.com/4818 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -344,6 +344,9 @@ static const struct speed_map stlink_khz_to_speed_map_jtag[] = {
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static void stlink_usb_init_buffer(void *handle, uint8_t direction, uint32_t size);
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static int stlink_swim_status(void *handle);
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void stlink_dump_speed_map(const struct speed_map *map, unsigned int map_size);
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static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map);
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static int stlink_speed(void *handle, int khz, bool query);
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/** */
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static unsigned int stlink_usb_block(void *handle)
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@ -1244,7 +1247,7 @@ static enum stlink_mode stlink_get_mode(enum hl_transports t)
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}
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/** */
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static int stlink_usb_init_mode(void *handle, bool connect_under_reset)
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static int stlink_usb_init_mode(void *handle, bool connect_under_reset, int initial_interface_speed)
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{
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int res;
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uint8_t mode;
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@ -1323,6 +1326,27 @@ static int stlink_usb_init_mode(void *handle, bool connect_under_reset)
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return ERROR_FAIL;
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}
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/* set the speed before entering the mode, as the chip discovery phase should be done at this speed too */
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if (h->transport == HL_TRANSPORT_JTAG) {
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if (h->version.flags & STLINK_F_HAS_JTAG_SET_FREQ) {
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stlink_dump_speed_map(stlink_khz_to_speed_map_jtag, ARRAY_SIZE(stlink_khz_to_speed_map_jtag));
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stlink_speed(h, initial_interface_speed, false);
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}
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} else if (h->transport == HL_TRANSPORT_SWD) {
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if (h->version.flags & STLINK_F_HAS_SWD_SET_FREQ) {
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stlink_dump_speed_map(stlink_khz_to_speed_map_swd, ARRAY_SIZE(stlink_khz_to_speed_map_swd));
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stlink_speed(h, initial_interface_speed, false);
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}
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}
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if (h->version.jtag_api == STLINK_JTAG_API_V3) {
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struct speed_map map[STLINK_V3_MAX_FREQ_NB];
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stlink_get_com_freq(h, (h->transport == HL_TRANSPORT_JTAG), map);
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stlink_dump_speed_map(map, ARRAY_SIZE(map));
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stlink_speed(h, initial_interface_speed, false);
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}
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/* preliminary SRST assert:
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* We want SRST is asserted before activating debug signals (mode_enter).
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* As the required mode has not been set, the adapter may not know what pin to use.
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@ -2814,7 +2838,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
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}
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/* initialize the debug hardware */
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err = stlink_usb_init_mode(h, param->connect_under_reset);
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err = stlink_usb_init_mode(h, param->connect_under_reset, param->initial_interface_speed);
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if (err != ERROR_OK) {
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LOG_ERROR("init mode failed (unable to connect to the target)");
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@ -2832,26 +2856,6 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
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return ERROR_OK;
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}
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if (h->transport == HL_TRANSPORT_JTAG) {
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if (h->version.flags & STLINK_F_HAS_JTAG_SET_FREQ) {
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stlink_dump_speed_map(stlink_khz_to_speed_map_jtag, ARRAY_SIZE(stlink_khz_to_speed_map_jtag));
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stlink_speed(h, param->initial_interface_speed, false);
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}
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} else if (h->transport == HL_TRANSPORT_SWD) {
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if (h->version.flags & STLINK_F_HAS_SWD_SET_FREQ) {
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stlink_dump_speed_map(stlink_khz_to_speed_map_swd, ARRAY_SIZE(stlink_khz_to_speed_map_swd));
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stlink_speed(h, param->initial_interface_speed, false);
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}
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}
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if (h->version.jtag_api == STLINK_JTAG_API_V3) {
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struct speed_map map[STLINK_V3_MAX_FREQ_NB];
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stlink_get_com_freq(h, (h->transport == HL_TRANSPORT_JTAG), map);
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stlink_dump_speed_map(map, ARRAY_SIZE(map));
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stlink_speed(h, param->initial_interface_speed, false);
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}
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/* get cpuid, so we can determine the max page size
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* start with a safe default */
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h->max_mem_packet = (1 << 10);
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