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XScale: restore_context() cleanup 

Clean up two aspects to this routine:  bad naming, since it
doesn't restore the context, just the banked registers; and
excess indentation for the bulk of the code.

Also make some of its call sites stash the function's return
code; someday they should use it for error checking.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-11-30 19:14:19 -08:00
parent da7c202b57
commit 892604bc7e
1 changed files with 30 additions and 38 deletions
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68
src/target/xscale.c
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@ -62,7 +62,7 @@
static int xscale_resume(struct target *, int current, static int xscale_resume(struct target *, int current,
uint32_t address, int handle_breakpoints, int debug_execution); uint32_t address, int handle_breakpoints, int debug_execution);
static int xscale_debug_entry(struct target *); static int xscale_debug_entry(struct target *);
static int xscale_restore_context(struct target *); static int xscale_restore_banked(struct target *);
static int xscale_get_reg(struct reg *reg); static int xscale_get_reg(struct reg *reg);
static int xscale_set_reg(struct reg *reg, uint8_t *buf); static int xscale_set_reg(struct reg *reg, uint8_t *buf);
static int xscale_set_breakpoint(struct target *, struct breakpoint *); static int xscale_set_breakpoint(struct target *, struct breakpoint *);
@ -1251,7 +1251,7 @@ static int xscale_resume(struct target *target, int current,
xscale_enable_single_step(target, next_pc); xscale_enable_single_step(target, next_pc);
/* restore banked registers */ /* restore banked registers */
xscale_restore_context(target); retval = xscale_restore_banked(target);
/* send resume request (command 0x30 or 0x31) /* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */ * clean the trace buffer if it is to be enabled (0x62) */
@ -1296,7 +1296,7 @@ static int xscale_resume(struct target *target, int current,
xscale_enable_watchpoints(target); xscale_enable_watchpoints(target);
/* restore banked registers */ /* restore banked registers */
xscale_restore_context(target); retval = xscale_restore_banked(target);
/* send resume request (command 0x30 or 0x31) /* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */ * clean the trace buffer if it is to be enabled (0x62) */
@ -1371,7 +1371,7 @@ static int xscale_step_inner(struct target *target, int current,
return retval; return retval;
/* restore banked registers */ /* restore banked registers */
if ((retval = xscale_restore_context(target)) != ERROR_OK) if ((retval = xscale_restore_banked(target)) != ERROR_OK)
return retval; return retval;
/* send resume request (command 0x30 or 0x31) /* send resume request (command 0x30 or 0x31)
@ -1755,7 +1755,7 @@ static int xscale_full_context(struct target *target)
return ERROR_OK; return ERROR_OK;
} }
static int xscale_restore_context(struct target *target) static int xscale_restore_banked(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_armv4_5(target);
@ -1774,8 +1774,8 @@ static int xscale_restore_context(struct target *target)
*/ */
for (i = 1; i < 7; i++) for (i = 1; i < 7; i++)
{ {
int dirty = 0;
enum armv4_5_mode mode = armv4_5_number_to_mode(i); enum armv4_5_mode mode = armv4_5_number_to_mode(i);
struct reg *r;
if (mode == ARMV4_5_MODE_USR) if (mode == ARMV4_5_MODE_USR)
continue; continue;
@ -1785,7 +1785,7 @@ static int xscale_restore_context(struct target *target)
{ {
if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
mode, j).dirty) mode, j).dirty)
dirty = 1; goto dirty;
} }
/* if not USR/SYS, check if the SPSR needs to be written */ /* if not USR/SYS, check if the SPSR needs to be written */
@ -1793,43 +1793,35 @@ static int xscale_restore_context(struct target *target)
{ {
if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
mode, 16).dirty) mode, 16).dirty)
dirty = 1; goto dirty;
} }
/* is there anything to flush for this mode? */ /* there's nothing to flush for this mode */
if (dirty) continue;
{
uint32_t tmp_cpsr;
struct reg *r;
/* command 0x1: "send banked registers" */ dirty:
xscale_send_u32(target, 0x1); /* command 0x1: "send banked registers" */
xscale_send_u32(target, 0x1);
tmp_cpsr = 0x0; /* send CPSR for desired mode */
tmp_cpsr |= mode; xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
tmp_cpsr |= 0xc0; /* I/F bits */
/* send CPSR for desired mode */ /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
xscale_send_u32(target, tmp_cpsr); * but this protocol doesn't understand that nuance.
*/
for (j = 8; j <= 14; j++) {
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
mode, j);
xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
r->dirty = false;
}
/* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */ /* send spsr if not in USR/SYS mode */
for (j = 8; j <= 14; j++) if (mode != ARMV4_5_MODE_SYS) {
{ r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, 16);
mode, j); xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
xscale_send_u32(target, r->dirty = false;
buf_get_u32(r->value, 0, 32));
r->dirty = false;
}
if (mode != ARMV4_5_MODE_SYS)
{
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
mode, 16);
xscale_send_u32(target,
buf_get_u32(r->value, 0, 32));
r->dirty = false;
}
} }
} }