interesting
/
riscv-openocd
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Report correct core instruction state for ARMv/A targets 

git-svn-id: svn://svn.berlios.de/openocd/trunk@2678 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
mlu 2009-09-08 15:32:18 +00:00
parent f6a5749c1b
commit 857c06ca8b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/armv7a.c
View File

@ -192,7 +192,7 @@ int armv7a_arch_state(struct target_s *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n" LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s", "MMU: %s, D-Cache: %s, I-Cache: %s",
armv7a_state_strings[armv4_5->core_state], armv7a_state_strings[armv7a->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name, target->debug_reason)->name,
armv7a_mode_strings[ armv7a_mode_strings[