target/riscv: set VLENB/MTOPI/MTOPEI existence on 0.11 targets
commit5f45b5bd73
("target/riscv: reg cache entry is initialized before access") introduced an assertion in `riscv_reg_impl_gdb_regno_exist()`. Link:f82c5a7c04/src/target/riscv/riscv_reg.c (L385-L389)
This assertion fails on RISC-V Debug Spec. 0.11 targets. The commit is intended to fix this. Change-Id: I20b56df1517f4071f4b6e39c83178a29a9cf95b0 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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@ -36,23 +36,50 @@ static const struct reg_arch_type *riscv011_gdb_regno_reg_type(uint32_t regno)
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return &riscv011_reg_type;
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return &riscv011_reg_type;
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}
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}
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static int riscv011_init_reg(struct target *target, uint32_t regno)
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{
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return riscv_reg_impl_init_cache_entry(target, regno,
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riscv_reg_impl_gdb_regno_exist(target, regno),
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riscv011_gdb_regno_reg_type(regno));
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}
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int riscv011_reg_init_all(struct target *target)
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int riscv011_reg_init_all(struct target *target)
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{
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{
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if (riscv_reg_impl_init_cache(target) != ERROR_OK)
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int res = riscv_reg_impl_init_cache(target);
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return ERROR_FAIL;
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if (res != ERROR_OK)
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return res;
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init_shared_reg_info(target);
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init_shared_reg_info(target);
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for (uint32_t regno = 0; regno < target->reg_cache->num_regs; ++regno)
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RISCV_INFO(r);
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if (riscv011_init_reg(target, regno) != ERROR_OK)
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assert(!r->vlenb
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return ERROR_FAIL;
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&& "VLENB discovery is not supported on RISC-V 0.11 targets");
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assert(!r->mtopi_readable
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&& "MTOPI discovery is not supported on RISC-V 0.11 targets");
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assert(!r->mtopei_readable
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&& "MTOPEI discovery is not supported on RISC-V 0.11 targets");
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/* Existence of some registers depends on others.
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* E.g. the presence of "v0-31" registers is infered from "vlenb" being
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* non-zero.
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* Currently, discovery of the following registers is not supported on
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* RISC-V 0.11 targets. */
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uint32_t non_discoverable_regs[] = {
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GDB_REGNO_VLENB,
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GDB_REGNO_MTOPI,
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GDB_REGNO_MTOPEI
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};
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for (unsigned int i = 0; i < ARRAY_SIZE(non_discoverable_regs); ++i) {
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const uint32_t regno = non_discoverable_regs[i];
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res = riscv_reg_impl_init_cache_entry(target, regno,
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/*exist*/ false, riscv011_gdb_regno_reg_type(regno));
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if (res != ERROR_OK)
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return res;
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}
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for (uint32_t regno = 0; regno < target->reg_cache->num_regs; ++regno) {
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const struct reg * const reg = riscv_reg_impl_cache_entry(target, regno);
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if (riscv_reg_impl_is_initialized(reg))
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continue;
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res = riscv_reg_impl_init_cache_entry(target, regno,
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riscv_reg_impl_gdb_regno_exist(target, regno),
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riscv011_gdb_regno_reg_type(regno));
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if (res != ERROR_OK)
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return res;
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}
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if (riscv_reg_impl_expose_csrs(target) != ERROR_OK)
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if (riscv_reg_impl_expose_csrs(target) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_FAIL;
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